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PDF KM416S4030CT-FH Data sheet ( Hoja de datos )

Número de pieza KM416S4030CT-FH
Descripción 1M x 16Bit x 4 Banks Synchronous DRAM
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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KM416S4030C
Revision History
Revision 1 (May 1998)
- ICC2N value (10mA) is changed to 12mA.
Revision .2 (June 1998)
- tSH (-10 binning) is revised.
Preliminary
CMOS SDRAM
REV. 2 June '98

1 page




KM416S4030CT-FH pdf
KM416S4030C
Preliminary
CMOS SDRAM
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, T A = 0 to 70 °C)
Parameter
Operating current
(One bank active)
Precharge standby current in
power-down mode
Precharge standby current in
non power-down mode
Active standby current in
power-down mode
Active standby current in
non power-down mode
(One bank active)
Operating current
(Burst mode)
Refresh current
Self refresh current
Symbol
Test Condition
Burst length = 1
ICC1 tRC tRC(min)
IOL = 0 mA
CAS
Latency -7
Version
Unit Note
-8 -H -L -10
75 75 70 70 65 mA 1
ICC2P CKE VIL(max), t CC = 15ns
ICC2PS CKE & CLK VIL(max), t CC =
1
mA
1
ICC2 N
CKE VIH(min), CS VIH(min), t CC = 15ns
Input signals are changed one time during 30ns
12
mA
ICC2 NS
CKE VIH(min), CLK VIL(max), t CC =
Input signals are stable
6
ICC3P CKE VIL(max), t CC = 15ns
ICC3PS CKE & CLK VIL(max), t CC =
2
mA
2
ICC3 N
CKE VIH(min), CS VIH(min), t CC = 15ns
Input signals are changed one time during 30ns
20
mA
ICC3 NS
CKE VIH(min), CLK VIL(max), t CC =
Input signals are stable
10 mA
IOL = 0 mA
ICC4
Page burst
2Banks activated
tCCD = 2CLKs
3 130 115 90 90 90
mA 1
2 90 90 90 85 85
ICC5 tRC tRC(min)
ICC6 CKE 0.2V
125
1
450
110 mA
mA
uA
2
3
4
Notes : 1. Measured with outputs open.
2. Refresh period is 64ms.
3. KM416S4030CT-G**
4. KM416S4030CT-F**
REV. 2 June '98

5 Page





KM416S4030CT-FH arduino
KM416S4030C
Preliminary
CMOS SDRAM
SIMPLIFIED TRUTH TABLE
Command
CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP
A11,
A9 ~ A0
Note
Register
Mode register set
H X LL LLX
OP code
1,2
Auto refresh
H
3
H
LL
LHX
X
Entry
L
3
Refresh
Self
refresh
Exit
LH HH
LH
X
X
3
HX X X
3
Bank active & row addr.
H
X LL HHX V
Row address
Read &
column address
Auto precharge disable
Auto precharge enable
H
X LH LHX V
L
Column
4
address
H
(A0 ~ A7)
4,5
Write &
column address
Auto precharge disable
Auto precharge enable
H
X LH L L X V
L
Column
4
address
H
(A0 ~ A7)
4,5
Burst stop
H X LH HL X X 6
Precharge
Bank selection
All banks
VL
H X LL HL X
XH
X
Clock suspend or
active power down
Entry
Exit
HX X X
HL
X
LV VV
L H XX XX X
X
Precharge power down mode
Entry
Exit
HX X X
HL
X
LH HH
HX X X
LH
X
LV VV
X
DQM
H X VX7
No operation command
HX X X
HX
X
LH HH
X
(V=Valid, X=Don t care, H=Logic high, L=Logic low)
Notes : 1. OP Code : Operand code
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA 0 and BA 1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA 0 is "Low" and BA 1 is "High" at read, write, row active and precharge, bank B is selected.
If both BA 0 is "High" and BA 1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA 0 and BA 1 are "High" at read, write, row active and precharge, bank D is selected.
If A 10/AP is "High" at row precharge, BA 0 and BA 1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t RP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
REV. 2 June '98

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