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PDF KESRX04 Data sheet ( Hoja de datos )

Número de pieza KESRX04
Descripción 260 to 470MHz. ASK Receiver with Power Down
Fabricantes Zarlink Semiconductor Inc 
Logotipo Zarlink Semiconductor Inc Logotipo



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KESRX04
260 to 470MHz. ASK Receiver with Power Down
Preliminary Information
DS4997 - 1.5 August 1998
The KESRX04 is a single chip ASK (Amplitude Shift Key)
Receiver IC. It is designed to operate in a variety of low power
radio applications including keyless entry, general domestic
and industrial remote control, RF tagging and local paging
systems.
The receiver offers an exceptionally high level of integration
and performance to meet the local oscillator radiation require-
ments of regulatory authorities world-wide. Functionally the
device works in the same way as the KESRX01 with the added
features of low supply voltage, in-band interference rejection
(anti-jamming detector), a 2 stage power down to enable
receiver systems to be implemented with less than 1mA supply,
and a wide IF bandwidth and drive stage to interface to an
external ceramic IF band pass filter at intermediate frequencies
from 0.2MHz to 15MHz.
The KESRX04 is an ideal receiver for difficult reception
areas where high level interferers would jam the wanted signal.
The anti-jamming circuit allows operation to be possible with
interfering signals which are more than 14dB stronger than the
wanted signal, without the cost penalties of increased IF
selectivity and frequency accuracy.
FEATURES
s In-band interference rejection (typ. 14dB)
s -103dBm Sensitivity (IF BW = 470kHz)
s AGC around LNA and Mixer
s Low supply voltage (3 to 6V)
s 2 stage power-down for low current applications
s Interface for ceramic IF filters up to 15MHz
IFFLT1
IFDC1
IFIN
IFDC2
VCC
IFOUT
VCCRF
MIXIP
RFOP
VEERF
RFIN
AGC
PEAK
DATOP
IFFLT2
RSSI
DETB
PD
XTAL1
XTAL2
DF0
DF1
DF2
VCO1
VCO2
VEE
LF
DSN
Figure 1 Pin Connections (top view)
QP28
APPLICATIONS
s Remote Keyless Entry
s Security, tagging
s Remote Controlled equipment
ORDERING INFORMATION
KESRX04/IG/QP1S (anti-static tubes)
KESRX04/IG/QP1T (tape and reel)
ABSOLUTE MAXIMUM RATINGS
Supply Voltage Vcc
-0.5V to +7V
Storage temperature,Tstg
-55 to 150°C
Junction Temperature, Tj
-55 to 150°C
RF Input power
+20dBm from 50
RF Input
agc
mixer
Ceramic
IF Filter
RSSI detector
SAW
Filter
LNA
Local
Oscillator
Noise
reduction
Filter
Anti-jam data filter Slicer
Sliced
data
Ref
Figure 2 Typical system application

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KESRX04 pdf
KESRX04
Notes:
1. The Sensitivity of the test fixture Figure 12 is degraded by loading the input to RF amplifier with 50 ohms, lack of image
rejection and increasing the data filter bandwidth to 50kHz. Sensitivity is defined as the average signal level measured
at the input necessary to achieve a bit error ratio of 0.01 where the input signal is a return to zero pulse at 470MHz.,with
an average duty cycle of 50%, 20kB/s data rate with the receiver bandwidth set to 470kHz.
2. Peak RF input level, pin RFIN, to overload the demodulator with the AGC operating. Equivalent to +7dBm for 50 ohm
input impedance. Where the input signal is a return to zero pulse at 470MHz. with an average duty cycle of 50%.
20kB/s data rate with the receiver bandwidth set to 470kHz.
3. Sensitivity is defined as the average signal level measured at the input necessary to achieve a bit error ratio of 0.01 where
the input signal is a return to zero pulse with an average duty cycle of 50%, 1kB/s data rate. Equivalent to -103dBm for
50ohm input impedance. Does not include insertion loss of SAW filter at RF input but does include IF filter of 470kHz
3dB bandwidth and a data filter bandwidth of 5kHz. This equates closely to a measurement of tangential sensitivity.
4. The performance of the power down option PD1 to PD2 cannot be guaranteed below 3V for temperatures less than 0°C
5. Time taken for PLL lock voltage to achieve 90% transition point of the control signal and the VCO frequency to achieve
within 470kHz of the final frequency. The time taken to acquire PLL acquisition is governed by the PLL loop filter (C12,
C1 and R2) and the crystal oscillator components (XTAL1, C13 and C14). The dominant term for PLL aquistion is the start-
up time of the crystal oscillator circuit, provided the PLL loop filter settling time is much less than the crystal oscillator start-
up time. Figure 6 illustrates a suitable test setup for measuring the acquisition time of the PLL. The electrical
characterisation parameters are based on the following set of conditions:
Crystal Oscillator circuit
C13 = C14 = 15pF
XTAL 1
Freq.
6.6128 MHz.
ESR
15.3
L 85.36 mH
C0 1.83 pF
C1 6.8 fF
PLL loop filter
C12 = 1.5 nF,
C1 = 180pF
R1 = 10K
6. Local oscillator power fed back into 50ohm source at antenna input (RF input). Measured with RF input matching network
shown in Figure 11.
7. In-band interference rejection for an unmodulated interfering signal at 100kHz. low side from the wanted modulated signal
at 433.92MHz. to achieve a Bit Error Rate =0.01. Figure 5 illustrates a suitable test set-up for measuring the interference
rejection and selectivity of the receiver.
Wanted signal =
(1kB/s. 50% duty cycle)
-90dBm at 433.92MHz.
Interfering signal =
(unmodulated)
-76dBm at 433.82MHz.
Interference rejection typically equals +14dBm.
i.e. in-band interfering signal is 14dBm above the wanted signal level at –90dBm.
8. Actual intermediate frequency determined by choice of crystal and external ceramic filter.
5

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KESRX04 arduino
KESRX04
90
80 Anti-jam
connected
70
60
50
40
30
20
10 Anti-jam
By-passed
0
-10
-20
431 431.5 432 432.5 433 433.5 434 434.5 435 435.5 436
Frequency Response (MHz.)
Figure 5b KESRX04 selectivity response
Note: The action of the anti-jam circuit to centre the bandwidth of the receiver around the wanted modulated signal at 433.92MHz
KESRX04 PCB
PLL
N/C N/C RFin RFGND
GND
Vcc DATA PD N/C
PLL
PLL
Spectrum Analyser
Oscilloscope 1
Power Down
Trigger
DC PSU (3 to 6V)
Power Down
Switch
GND
t
Figure 6 Characterising the PLL aquisition time from power-up
Note :
1 High impedance (*10 probe) oscilloscope probe recommended
2 Loosely coupled antenna or high impedance FET probe recommended for the spectrum analyser measurement.
3 Time taken for PLL to achieve 90% of final voltage and the VCO within +/- 470kHz. of final frequency (423.33MHz.)
4 Power down switch operation.
PD0 = PD pin connected to GND, receiver fully powered down.
PD1 = PD pin open circuit or connected to Vcc/2, crystal oscillator running.
PD2 = PD pin connected to Vcc, receiver fully operational.
5. Spectrum analyser set to PLL lock frequency (423.33MHz), zero span 470kHz IF bandwidth, t sweep 20mS.
11

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