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PDF IDT74FCT621TSO Data sheet ( Hoja de datos )
| Número de pieza | IDT74FCT621TSO | |
| Descripción | FAST CMOS OCTAL BUS TRANSCEIVER (OPEN DRAIN) | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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IDT54/74FCT621T/AT
FAST CMOS OCTAL BUS TRANSCEIVER (OPEN DRAIN)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FAST CMOS
IDT54/74FCT621T/AT
OCTAL BUS TRANSCEIVER
Integrated Device Technology, Inc.
(OPEN DRAIN)
FEATURES:
• Std. and A speed grades
• Low input and output leakage ≤1µA (max.)
• CMOS power levels
• True TTL input and output compatibility
– VOH = 3.3V (typ.)
– VOL = 0.3V (typ.)
• Power off disable outputs permit “live insertion”
• Meets or exceeds JEDEC standard 18 specifications
• Product available in Radiation Tolerant and Radiation
Enhanced versions
• Military product compliant to MIL-STD-883, Class B
and DESC listed (dual marked)
• Available in DIP, SOIC, CERPACK and LCC packages
DESCRIPTION:
The IDT54/74FCT621T/AT is an octal transceiver with
non-inverting Open-Drain bus compatible outputs in both
send and receive directions. The B bus outputs are capable
of sinking 64mA providing very good capacitive drive
characteristics. These octal bus transceivers are designed for
asynchronous two-way communication between data buses.
The control function implementation allows for maximum
flexibility in timing.
FUNCTIONAL BLOCK DIAGRAM (1)
GBA
GAB
A1
B1
A2 –A8
B 2 –B 8
7 Other Transceivers
2538 drw 01
PIN CONFIGURATIONS
GAB
A1
A2
A3
A4
A5
A6
A7
A8
GND
1
2
3
4
P20-1,
D20-1,
5 SO20-2
6&
7 E20-1
8
9
10
20
19
18
17
16
15
14
13
12
11
Vcc
GBA
B1
B2
B3
B4
B5
B6
B7
B8
2538 drw 02
DIP/SOIC/CERPACK
TOP VIEW
INDEX
32
20 19
A3 4
1 18 B1
A4 5
17 B2
A5 6 L20-2 16 B3
A6 7
15 B4
A7 8
14 B5
9 10 11 12 13
2538 drw 03
The IDT logo is a registered trademark of Integreted Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1995 Integrated Device Technology, Inc.
66..1188
LCC
TOP VIEW
APRIL 1994
DSC-42122/4
1
1 page  
IDT54/74FCT621T/AT
FAST CMOS OCTAL BUS TRANSCEIVER (OPEN DRAIN)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
V CC
7.0V
VIN
Pulse
Generator
D.U.T.
RT
VOUT
50pF
CL
500Ω
500Ω
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
Closed
Enable Low
All Other Tests
Open
DEFINITIONS:
2538 lnk 08
CL= Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
2538 drw 03
SET-UP, HOLD AND RELEASE TIMES
PULSE WIDTH
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONTROL
PRESET
CLEAR
CLOCK ENABLE
ETC.
tSU
tSU
tH
tREM
tH
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
2538 drw 04
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
tW
1.5V
1.5V
2538 drw 05
PROPAGATION DELAY
SAME PHASE
INPUT TRANSITION
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
tPLH
tPLH
tPHL
tPHL
ENABLE AND DISABLE TIMES
3V
1.5V
0V
VOH
1.5V
VOL
3V
1.5V
0V
2538 drw 06
ENABLE
CONTROL
INPUT
OUTPUT
NORMALLY
LOW
tPZL
SWITCH
CLOSED
tPZH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
DISABLE
tPLZ
3.5V
1.5V
0.3V
tPHZ
1.5V
0V
0.3V
3V
1.5V
0V
3.5V
VOL
VOH
0V
2538 drw 07
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns
6.18 5
5 Page | ||
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| PDF Descargar | [ Datasheet IDT74FCT621TSO.PDF ] | |
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