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PDF IDT74FCT3807APYI Data sheet ( Hoja de datos )

Número de pieza IDT74FCT3807APYI
Descripción 3.3V CMOS 1-TO-10 CLOCK DRIVER
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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IDT74FCT3807/A
3.3V CMOS 1-TO-10 CLOCK DRIVER
COMMERCIAL/INDUSTRIALTEMPERATURERANGES
3.3V CMOS
1-TO-10 CLOCK DRIVER
IDT74FCT3807/A
FEATURES:
• 0.5 MICRON CMOS Technology
• Guaranteed low skew < 350ps (max.)
• Very low duty cycle distortion < 350ps (max.)
• High speed: propagation delay < 3ns (max.)
• Very low CMOS power levels
• TTL compatible inputs and outputs
• 1:10 fanout
• Maximum output rise and fall time < 1.5ns (max.)
• Low input capacitance: 4.5pF typical
• VCC = 3.3V ± 0.3V
• Inputs can be driven from 3.3V or 5V components
• Available in SSOP, SOIC, and QSOP packages
DESCRIPTION:
The FCT3807/A 3.3V clock driver is built using advanced dual metal CMOS
technology. Thislowskewclockdriveroffers1:10fanout. Thelargefanoutfrom
a single input reduces loading on the preceding driver and provides an efficient
clockdistributionnetwork. TheFCT3807/Aofferslowcapacitanceinputswith
hysteresis for improved noise margins. Multiple power and grounds reduce
noise. Typical applications are clock and signal distribution.
FUNCTIONAL BLOCK DIAGRAM
O1
O2
O3
O4
O5
IN
O6
O7
O8
O9
O10
PIN CONFIGURATION
IN
GND
O1
VCC
O2
GND
O3
VCC
O4
GND
1
2
3
4
5
6
7
8
9
10
20 VCC
19 O10
18 O9
17 GND
16 O8
15 VCC
14 O7
13 GND
12 O6
11 O5
SOIC/ SSOP/ QSOP
TOP VIEW
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL/INDUSTRIAL TEMPERATURE RANGES
c 2001 Integrated Device Technology, Inc.
1
SEPTEMBER 2001
DSC-4647/2

1 page




IDT74FCT3807APYI pdf
IDT74FCT3807/A
3.3V CMOS 1-TO-10 CLOCK DRIVER
COMMERCIAL/INDUSTRIALTEMPERATURERANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - INDUSTRIAL(3,4)
FCT3807
FCT3807A
Symbol Parameter
Conditions(1)
Min.(2)
Max.
Min.(2)
Max. Unit
tPLH PropagationDelay
50to VCC/2
1.5
3.5
1.5
3 ns
tPHL CL = 10pF
tR OutputRiseTime
(See figure 1)
1.5
— 1.5 ns
tF OutputFallTime
or 50AC
1.5
— 1.5 ns
tSK(O) Output skew: skew between outputs of
termination,
0.6
— 0.45 ns
same package (same transition)
CL = 10pF
tSK(P) Pulse skew: skew between opposite transitions
(See figure 2)
0.6
— 0.45 ns
of same output (|tPHL-–tPLH|)
f 100MHz
tSK(T) Package skew: skew between outputs of different
Outputs
0.9
— 0.65 ns
packages at same power supply voltage,
connected in
temperature, package type and speed grade
groups of two
Symbol
tPLH
tPHL
tR
tF
tSK(O)
tSK(P)
tSK(T)
Parameter
Propagation Delay
Output Rise Time
Output Fall Time
Output skew: skew between outputs of
same package (same transition)
Pulse skew: skew between opposite transitions
of same output (|tPHL-–tPLH|)
Package skew: skew between outputs of different
packages at same power supply voltage,
temperature, package type and speed grade
Conditions(1)
CL = 30pF
f 67MHz
(See figure 3)
FCT3807
Min.(2)
Max.
1.5 4.5
— 1.5
— 1.5
— 0.6
— 0.6
—1
FCT3807A
Min.(2)
Max.
1.5 4
— 1.5
— 1.5
— 0.45
— 0.45
— 0.75
Unit
ns
ns
ns
ns
ns
ns
Symbol
tPLH
tPHL
tR
tF
tSK(O)
tSK(P)
Parameter
Propagation Delay
Output Rise Time
Output Fall Time
Output skew: skew between outputs of
same package (same transition)
Pulse skew: skew between opposite transitions
of same output (|tPHL-–tPLH|)
Conditions(1)
CL = 50pF
f 40MHz
(See figure 4)
FCT3807
Min.(2)
Max.
1.5 4.8
— 1.5
— 1.5
— 0.6
— 0.6
FCT3807A
Min.(2)
Max.
1.5 4.3
— 1.5
— 1.5
— 0.45
— 0.45
Unit
ns
ns
ns
ns
ns
tSK(T) Package skew: skew between outputs of different
—1
— 0.75 ns
packages at same power supply voltage,
temperature, package type and speed grade
NOTES:
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. tPLH, tPHL, tSK(t) are production tested. All other parameters guaranteed but not production tested.
4. Propagation delay range indicated by Min. and Max. limit is due to VCC, operating temperature and process parameters. These propagation delay limits do not imply skew.
5

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