DataSheet.es    


PDF IDT71342 Data sheet ( Hoja de datos )

Número de pieza IDT71342
Descripción HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



Hay una vista previa y un enlace de descarga de IDT71342 (archivo pdf) en la parte inferior de esta página.


Total 13 Páginas

No Preview Available ! IDT71342 Hoja de datos, Descripción, Manual

Integrated Device Technology, Inc.
HIGH-SPEED
4K x 8 DUAL-PORT
STATIC RAM WITH SEMAPHORE
IDT71342SA/LA
FEATURES:
• High-speed access
— Commercial: 20/25/35/45/55/70ns (max.)
• Low-power operation
— IDT71342SA
Active: 500mW (typ.)
Standby: 5mW (typ.)
— IDT71342LA
Active: 500mW (typ.)
Standby: 1mW (typ.)
• Fully asynchronous operation from either port
• Full on-chip hardware support of semaphore signalling
between ports
• Battery backup operation—2V data retention
• TTL-compatible; single 5V (±10%) power supply
• Available in plastic packages
• Industrial temperature range (–40°C to +85°C) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT71342 is an extremely high-speed 4K x 8 Dual-Port
Static RAM with full on-chip hardware support of semaphore
signalling between the two ports.
The IDT71342 provides two independent ports with separate
control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. To assist in arbitrating between ports, a fully
independent semaphore logic block is provided. This block
contains unassigned flags which can be accessed by either
side; however, only one side can control the flag at any time.
An automatic power down feature, controlled by CE and SEM,
permits the on-chip circuitry of each port to enter a very low
standby power mode (both CE and SEM High).
Fabricated using IDT’s CMOS high-performance
technology, this device typically operates on only 500mW of
power. Low-power (LA) versions offer battery backup data
retention capability, with each port typically consuming 200µW
from a 2V battery. The device is packaged in either a 64-pin
TQFP, thin quad plastic flatpack, or a 52-pin PLCC.
FUNCTIONAL BLOCK DIAGRAM
R/ WL
CEL
R/ WR
CER
OEL
I/O0L- I/O7L
COLUMN
I/O
COLUMN
I/O
OER
I/O0R - I/O7R
MEMORY
ARRAY
SEML
A0L- A11L
SEMAPHORE
LOGIC
LEFT SIDE
ADDRESS
DECODE
LOGIC
RIGHT SIDE
ADDRESS
DECODE
LOGIC
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
6.05
SEMR
A0R- A11R
2721 drw 01
OCTOBER 1996
DSC-2721/4
1

1 page




IDT71342 pdf
IDT71342SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(4)
Symbol
Parameter
READ CYCLE
tRC Read Cycle Time
tAA
tACE
Address Access Time
Chip Enable Access Time(3)
tAOE
Output Enable Access Time
tOH
tLZ
tHZ
tPU
tPD
tSOP
tWDD
tDDD
Output Hold from Address Change
Output Low-Z Time(1, 2)
Output High-Z Time(1, 2)
Chip Enable to Power Up Time(2)
Chip Disable to Power Down Time(2)
SEM Flag Update Pulse (OE or SEM)
Write Pulse to Data Delay(4)
Write Data Valid to Read Data Delay(4)
tSAA Semaphore Address Access Time
71342X20
Min.
Max.
20 —
— 20
— 20
— 15
0—
0—
— 15
0—
— 50
——
— 40
— 30
——
COMMERCIAL TEMPERATURE RANGE
71342X25
Min.
Max.
25 —
— 25
— 25
— 15
0—
0—
— 15
0—
— 50
10 —
— 50
— 30
— 25
71342X35
Min. Max.
Unit
35 — ns
— 35 ns
— 35 ns
— 20 ns
0 — ns
0 — ns
— 20 ns
0 — ns
— 50 ns
15 — ns
— 60 ns
— 35 ns
— 35 ns
2721 tbl 09
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE(4) (CONT'D)
Symbol
Parameter
READ CYCLE
tRC Read Cycle Time
tAA
tACE
Address Access Time
Chip Enable Access Time(3)
tAOE
Output Enable Access Time
tOH Output Hold from Address Change
tLZ Output Low-Z Time(1, 2)
tHZ Output High-Z Time(1, 2)
tPU Chip Enable to Power Up Time(2)
tPD
tSOP
tWDD
tDDD
Chip Disable to Power Down Time(2)
SEM Flag Update Pulse (OE or SEM)
Write Pulse to Data Delay(4)
Write Data Valid to Read Data Delay(4)
tSAA Semaphore Address Access Time
71342X45
Min.
Max.
45 —
— 45
— 45
— 25
0—
5—
— 20
0—
— 50
15 —
— 70
— 45
— 45
71342X55
Min. Max.
55 —
— 55
— 55
— 30
0—
5—
— 25
0—
— 50
20 —
— 80
— 55
— 55
NOTES:
1. Transition is measured ±500mV from Low or High-impedance voltage with the Ouput Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH, and SEM = VIL.
4. “X” in part number indicates power rating (SA or LA).
71342X70
Min. Max. Unit
70 — ns
— 70 ns
— 70 ns
— 40 ns
0 — ns
5 — ns
— 30 ns
0 — ns
— 50 ns
20 — ns
— 90 ns
— 70 ns
— 70 ns
2721 tbl 10
6.05 5

5 Page





IDT71342 arduino
IDT71342SA/LA
HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHORE
COMMERCIAL TEMPERATURE RANGE
processor writes a zero in the left port at a free semaphore
location. On a subsequent read, the processor will verify that
it has written successfully to that location and will assume
control over the resource in question. Meanwhile, if a processor
on the right side attempts to write a zero to the same semaphore
flag it will fail, as will be verified by the fact that a one will be
read from that semaphore on the right side during a subsequent
read. Had a sequence of READ/WRITE been used instead,
system contention problems could have occurred during the
gap between the read and write cycles.
It is important to note that a failed semaphore request must
be followed by either repeated reads or by writing a one into
the same location. The reason for this is easily understood by
looking at the simple logic diagram of the semaphore flag in
Figure 3. Two semaphore request latches feed into a
semaphore flag. Whichever latch is first to present a zero to
the semaphore flag will force its side of the semaphore flag low
and the other side high. This condition will continue until a one
is written to the same semaphore request latch. Should the
other side’s semaphore request latch have been written to a
zero in the meantime, the semaphore flag will now stay low
until its semaphore request latch is written to a one. From this
it is easy to understand that, if a semaphore is requested and
the processor which requested it no longer needs the resource,
the entire can hang up until a one is written into that semaphore
request latch.
The critical case of semaphore timing is when both sides
request a single token by attempting to write a zero into it at
the same time. The semaphore logic is specially designed to
resolve this problem. If simultaneous requests are made, the
logic guarantees that only one side receives the token. If one
side is earlier than the other in making the request, the first
TABLE I — NON-CONTENTION READ/WRITE CONTROL
Left or Right Port(1)
R/W CE SEM OE D0-7
Function
X H H X Z Port Disabled and in Power Down Mode
H H L L DATAOUT Data in Semaphore Flag Output on Port
X X X H Z Output Disabled
uH
L
X
DATAIN
Port Data Bit D0 Written Into Semaphore Flag
H L H L DATAOUT Data in Memory Output on Port
L
L
H
X
DATAIN
Data on Port Written Into Memory
X L L X — Not Allowed
NOTE:
1. AOL = A10L A0R - A10R.
u"H" = HIGH, "L" = LOW, "X" = Don’t Care, "Z" = High-impedance, and " " = Low-to-High transition.
2721 tbl 13
TABLE II — EXAMPLE SEMAPHORE PROCUREMENT SEQUENCE(1,2)
Function
No Action
D0 - D7 Left
1
D0 - D7 Right
1
Semaphore free
Status
Left Port Writes “0” to Semaphore
0
1 Left port has semaphore token
Right Port Writes “0” to Semaphore
0
1 No change. Right side has no write access to semaphore
Left Port Writes “1” to Semaphore
1
0 Right port obtains semaphore token
Left Port Writes “0” to Semaphore
1
0 No change. Left side has no write access to semaphore
Right Port Writes “1” to Semaphore
0
1 Left port obtains semaphore token
Left Port Writes “1” to Semaphore
1
1 Semaphore free
Right Port Writes “0” to Semaphore
1
0 Right port has semaphore token
Right Port Writes “1” to Semaphore
1
1 Semaphore free
Left Port Writes “0” to Semaphore
0
1 Left port has semaphore token
Left Port Writes “1” to Semaphore
1
1 Semaphore free
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT71342.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O7). These eight semaphores are addressed by A0 - A2.
2721 tbl 14
6.05 11

11 Page







PáginasTotal 13 Páginas
PDF Descargar[ Datasheet IDT71342.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
IDT7134HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHOREIntegrated Device Technology
Integrated Device Technology
IDT71342HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHOREIntegrated Device Technology
Integrated Device Technology
IDT71342LAHIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHOREIntegrated Device Technology
Integrated Device Technology
IDT71342SAHIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM WITH SEMAPHOREIntegrated Device Technology
Integrated Device Technology

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar