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PDF IDT7133 Data sheet ( Hoja de datos )

Número de pieza IDT7133
Descripción HIGH-SPEED 2K x 16 CMOS DUAL-PORT STATIC RAMS
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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HIGH SPEED
2K X 16 DUAL-PORT
SRAM
IDT7133SA/LA
IDT7143SA/LA
Features
High-speed access
– Military: 35/55/70/90ns (max.)
– Industrial: 25/55ns (max.)
– Commercial: 20/25/35/45/55/70/90ns (max.)
Low-power operation
– IDT7133/43SA
Active: 1150mW (typ.)
Standby: 5mW (typ.)
– IDT7133/43LA
Active: 1050mW (typ.)
Standby: 1mW (typ.)
Versatile control for write: separate write control for lower
and upper byte of each port
Functional Block Diagram
R/WLUB
CEL
MASTER IDT7133 easily expands data bus width to 32 bits
or more using SLAVE IDT7143
On-chip port arbitration logic (IDT7133 only)
BUSY output flag on IDT7133; BUSY input on IDT7143
Fully asynchronous operation from either port
Battery backup operation–2V data retention
TTL-compatible; single 5V (±10%) power supply
Available in 68-pin ceramic PGA, Flatpack, PLCC and 100-
pin TQFP
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
R/WRUB
CER
R/WLLB
OEL
R/WRLB
OER
I/O8L - I/O15L
I/O0L - I/O7L
BUSYL(1)
A10L
A0L
I/O
CONTROL
I/O
CONTROL
ADDRESS
DECODER
11
CEL
MEMORY
ARRAY
ARBITRATION
LOGIC
(IDT7133 ONLY)
ADDRESS
DECODER
11
CER
I/O8R - I/O15R
I/O0R - I/O7R
BUSY R(1)
A10R
A0R
NOTE:
1. IDT7133 (MASTER): BUSY is open drain output and requires pull-up resistor.
IDT7143 (SLAVE): BUSY is input.
2746 drw 01
©2013 Integrated Device Technology, Inc.
1
JANUARY 2012
DSC 2746/14

1 page




IDT7133 pdf
IDT7133SA/LA, IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM
Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Operating
Temperature and Supply Voltage Range(2) (VCC = 5.0V ± 10%)
Symbol
Parameter
ICC Dynamic Operating
Current
(Both Ports Active)
Test Condition
CE = VIL, Outputs Disabled
f = fMAX(3)
ISB1 Standby Current
(Both Ports - TTL
Level Inputs)
CEL and CER = VIH
f = fMAX(3)
ISB2 Standby Current
(One Port - TTL
Level Inputs)
CE"A" = VIL and CE"B" = VIH(4)
f=fMAX(3)
Active Port Outputs Disabled
ISB3 Full Standby Current
(Both Ports -
CMOS Level Inputs)
ISB4 Full Standby Current
(One Port -
CMOS Level Inputs)
Both Ports CEL and
CER > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(4)
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(5)
VIN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Disabled
f = fMAX(3)
Version
COM'L
S
L
MIL &
IND
S
L
COM'L
S
L
MIL &
IND
S
L
COM'L
S
L
MIL &
IND
S
L
COM'L
S
L
MIL &
IND
S
L
COM'L
S
L
MIL &
IND
S
L
7133X20
7143X20
Com'l Only
Typ.(1)
250
230
____
____
Max.
310
280
____
____
25 80
25 70
____ ____
____ ____
140 200
120 180
____ ____
____ ____
1.0 15
0.2 5
____ ____
____ ____
140 190
120 170
____ ____
____ ____
7133X25
7143X25
Com'l & Ind
Typ.(1)
250
230
250
230
25
25
25
25
140
100
140
100
1.0
0.2
1.0
0.2
140
120
140
120
Max.
300
270
330
300
80
70
90
80
200
170
230
190
15
4
30
10
190
170
220
200
7133X35
7143X35
Com'l
& Military
Typ.(1) Max.
240 295
210 250
240 325
220 295
25 70
25 60
25 75
25 65
120 180
100 160
120 200
100 180
1.0 15
0.2 4
1.0 30
0.2 10
120 170
100 150
120 190
100 170
Unit
mA
mA
mA
mA
mA
2746 tbl 07a
Symbol
Parameter
ICC Dynamic Operating
Current
(Both Ports Active)
Test Condition
CE = VIL, Outputs Disabled
f = fMAX(3)
ISB1 Standby Current
(Both Ports - TTL
Level Inputs)
CEL and CER = VIH
f = fMAX(3)
ISB2 Standby Current
(One Port - TTL
Level Inputs)
CE"A" = VIL and CE"B" = VIH(4)
f=fMAX(3)
Active Port Outputs Disabled
ISB3 Full Standby Current
(Both Ports -
CMOS Level Inputs)
ISB4 Full Standby Current
(One Port -
CMOS Level Inputs)
Both Ports CEL and
CER > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(4)
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(5)
VIN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Disabled
f = fMAX(3)
Version
COM'L
S
L
MIL &
IND
S
L
COM'L
S
L
MIL &
IND
S
L
COM'L
S
L
MIL &
IND
S
L
COM'L
S
L
MIL &
IND
S
L
COM'L
S
L
MIL &
IND
S
L
7133X45
7143X45
Com'l Only
Typ.(1)
230
210
____
____
Max.
290
250
____
____
25 75
25 65
____ ____
____ ____
120 190
100 170
____ ____
____ ____
1.0 15
0.2 4
____ ____
____ ____
120 180
100 160
____ ____
____ ____
7133X55
7143X55
Com'l, Ind
& Military
Typ.(1) Max.
230 285
210 250
230 315
210 285
25 70
25 60
25 80
25 70
120 180
100 160
120 210
100 190
1.0 15
0.2 4
1.0 30
0.2 10
120 170
100 150
120 200
100 180
7133X70/90
7143X70/90
Com'l &
Military
Typ.(1) Max.
230 280
210 250
230 310
210 280
25 70
25 60
25 75
25 65
120 180
100 160
120 200
100 180
1.0 15
0.2 4
1.0 30
0.2 10
120 170
100 150
120 190
100 170
Unit
mA
mA
mA
mA
mA
2746 tbl 07b
NOTES:
1. VCC = 5V, TA = +25°C for Typ., and are not production tested. ICCDC = 180mA (typ.)
2. 'X' in part number indicates power rating (SA or LA)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC, and using “AC Test Conditions" of input levels of
GND to 3V.
4. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6.542

5 Page





IDT7133 arduino
IDT7133SA/LA, IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1 (R/W Controlled Timing)(1,5,8)
ADDRESS
tWC
OE
CE
R/W (9)
DATAOUT
DATAIN
tAS(6)
tLZ
tAW
tWP(2)
tWZ (7)
(4)
tWR(3)
tOW
tDW
tDH
tHZ(7)
tHZ (7)
(4)
2746 drw 09
Write Cycle No. 2 (CE Controlled Timing)(1,5)
ADDRESS
CE
R/W (9)
DATAIN
tAS(6)
tWC
tAW
tEW (2)
tDW
tWR
tDH
2746 drw 10
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL.
3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle.
4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. Timing depends on which enable signal is de-asserted first, CE or OE.
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed
on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified tWP.
9. R/W for either upper or lower byte.
61.412

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