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PDF IDT71256SA70TP Data sheet ( Hoja de datos )
| Número de pieza | IDT71256SA70TP | |
| Descripción | CMOS STATIC RAM 256K (32K x 8-BIT) | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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Integrated Device Technology, Inc.
CMOS STATIC RAM
256K (32K x 8-BIT)
IDT71256SA70
FEATURES:
• 32K x 8 CMOS static RAM
• Equal access and cycle times
-- Commercial: 70ns
• One Chip Select plus one Output Enable pin
• Bidirectional data inputs and outputs directly
TTL-compatible
• Low power consumption via chip deselect
• Available in 28-pin 30 mil Plastic SOJ, 28-pin 300 mil
Plastic Dip, 28-pin 300 mil TSOP Type I, and 28-pin 600
mil Plastic Dip.
DESCRIPTION:
The IDT71256SA is a 262,144-bit medium-speed Static
RAM organized as 32K x 8. It is fabricated using IDT’s high-
perfomance, high-reliability CMOS technology. This state-of-
the-art technology, combined with innovative circuit design
techniques, provides a cost-effective solution for your memory
needs.
All bidirectional inputs and outputs of the IDT71256SA are
TTL-compatible and operation is from a single 5V supply.
Fully static asynchronous circuitry is used, requiring no clocks
or refresh for operation.
The IDT71256SA is packaged in a 28-pin 300 mil Plastic
SOJ, 28-pin 300 mil Plastic Dip, 28-pin 300 mil TSOP Type I
and 28-pin 600 mil Plastic Dip.
FUNCTIONAL BLOCK DIAGRAM
A0
A14
I/O 0
I/O 7
CS
OE
WE
ADDRESS
DECODER
INPUT
DATA
CIRCUIT
CONTROL
CIRCUIT
262,144 BIT
MEMORY ARRAY
I/O CONTROL
V CC
GND
3567 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
JULY 1996
3567/1
1
1 page  
IDT71256SA70
CMOS STATIC RAM 256K (32K x 8-BIT)
COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)
ADDRESS
tRC
tAA
tOH
tOH
DATAOUT
PREVIOUS DATAOUT VALID
DATAOUT VALID
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
3567 drw 07
TIMING WAVEFORM OF WRITE CYCLE NO.1 (WE CONTROLLED TIMING)(1,2,3,5)
ADDRESS
CS
WE
DATAOUT
DATAIN
tWC
tAW
tAS
tWP(3)
tWR
tWHZ (6)
tOW (6)
(4) HIGH IMPEDANCE
tDH
tDW
DATAIN VALID
tCHZ (6)
(4)
3567 drw 08
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CS CONTROLLED TIMING)(1,2,5)
tWC
ADDRESS
tAW
CS
tAS
tCW tWR
WE
tDW tDH
DATAIN
DATAIN VALID
NOTES:
1. WE or CS must be HIGH during all address transitions.
3567 drw 09
2. A write occurs during the overlap of a LOW CS and a LOW WE.
3. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn
off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the
minimum write pulse is as short as the specified tWP.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
6. Transition is measured ±200mV from steady state.
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet IDT71256SA70TP.PDF ] | |
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