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PDF IDT71256 Data sheet ( Hoja de datos )
| Número de pieza | IDT71256 | |
| Descripción | CMOS STATIC RAM 256K (32K x 8-BIT) | |
| Fabricantes | Integrated Device Technology | |
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CMOS Static RAM
256K (32K x 8-Bit)
IDT71256S
IDT71256L
Features
◆ High-speed address/chip select time
– Military: 25/35/45/55/70/85/100ns (max.)
– Commercial/Industrial: 20/25/35ns (max.) low power only
◆ Low-power operation
◆ Battery Backup operation – 2V data retention
◆ Produced with advanced high-performance CMOS
technology
◆ Input and output directly TTL-compatible
◆ Available in standard 28-pin (300 or 600 mil) ceramic DIP,
28-pin (300 mil) SOJ
◆ Military product compliant to MIL-STD-883, Class B
Description
The IDT 71256 is a 262,144-bit high-speed static RAM organized as
32K x 8. It is fabricated using high-performance, high-reliability CMOS
technology.
Address access times as fast as 20ns are available with power
consumption of only 350mW (typ.). The circuit also offers a reduced power
standby mode. When CS goes HIGH, the circuit will automatically go to and
remainin,alow-powerstandbymodeaslongasCS remainsHIGH. This
capability provides significant system level power and cooling savings.
The low-power (L) version also offers a battery backup data retention
capability where the circuit typically consumes only 5μW when operating
off a 2V battery.
The IDT71256 is packaged in a 28-pin (300 or 600 mil) ceramic DIP,
a 28-pin 300 mil SOJ providing high board level packing densities.
The IDT71256 military RAM is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally suited to military
temperature applications demanding the highest level of performance and
reliability.
Functional Block Diagram
A0
ADDRESS
DECODER
A14
I/O0
INPUT
DATA
CIRCUIT
I/O7
CS
OE CONTROL
WE CIRCUIT
262,144 BIT
MEMORY ARRAY
I/O CONTROL
VCC
GND
,
2946 drw 01
©2013 Integrated Device Technology, Inc.
1
SEPTEMBER 2013
DSC-2946/13
1 page  
IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
Low VCC Data Retention Waveform
DATA
RETENTION
MODE
VCC 4.5V
4.5V
tCDR
VDR ≥ 2V
tR
CS VIH
VIH
VDR
2946 drw 06
AC Electrical Characteristics (VCC = 5.0V ± 10%, All Temperature Ranges)
71256L20(1)
71256S25(3)
71256L25
71256S35(3)
71256L35
71256S45(3)
71256L45(3)
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max.
Unit
Read Cycle
tRC Read Cycle Time
20 ____ 25 ____ 35 ____ 45 ____ ns
tAA Address Access Time
____ 20 ____ 25 ____ 35 ____ 45 ns
tACS Chip Select Access Time
____ 20 ____ 25 ____ 35 ____ 45 ns
tCLZ(2)
Chip Select to Output in Low-Z
5 ____ 5 ____ 5 ____ 5 ____ ns
tCHZ(2)
Chip Deselect to Output in High-Z
____ 10 ____ 11 ____ 15 ____ 20 ns
tOE Output Enable to Output Valid
____ 10 ____ 11 ____ 15 ____ 20 ns
tOLZ(2)
Output Enable to Output in Low-Z
2 ____ 2 ____ 2 ____ 0 ____ ns
tOHZ(2)
Output Disable to Output in High-Z
2 8 2 10 2 15 ____ 20 ns
tOH Output Hold from Address Change
5 ____ 5 ____ 5 ____ 5 ____ ns
Write Cycle
tWC Write Cycle Time
20 ____ 25 ____ 35 ____ 45 ____ ns
tCW Chip Select to End-of-Write
15 ____ 20 ____ 30 ____ 40 ____ ns
tAW Address Valid to End-of-Write
15 ____ 20 ____ 30 ____ 40 ____ ns
tAS Address Set-up Time
0 ____ 0 ____ 0 ____ 0 ____ ns
tWP Write Pulse Width
15 ____ 20 ____ 30 ____ 35 ____ ns
tWR Write Recovery Time
0 ____ 0 ____ 0 ____ 0 ____ ns
tDW Data to Write Time Overlap
11 ____ 13 ____ 15 ____ 20 ____ ns
tWHZ(2)
Write Enable to Output in High-Z
____ 10 ____ 11 ____ 15 ____ 20 ns
tDH Data Hold from Write Time
0 ____ 0 ____ 0 ____ 0 ____ ns
tOW(2)
Output Active from End-of-Write
5 ____ 5 ____ 5 ____ 5 ____ ns
NOTES:
1. 0° to +70°C or -40° to +85°C temperature range only.
2. This parameter is guaranteed by device characterization, but is not production tested.
3. –55°C to +125°C temperature range only.
2946 tbl 12
6.452
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| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet IDT71256.PDF ] | |
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