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PDF IDT71215S8PF Data sheet ( Hoja de datos )

Número de pieza IDT71215S8PF
Descripción BiCMOS StaticRAM 240K (16K x 15-BIT) CACHE-TAG RAM For the PentiumO Processor
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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Integrated Device Technology, Inc.
BiCMOS StaticRAM
240K (16K x 15-BIT)
CACHE-TAG RAM
For the PentiumProcessor
IDT71215
FEATURES:
• 16K x 15 Configuration
– 12 TAG Bits
– 3 Separate I/O Status Bits (Valid, Dirty, Write Through)
• Match output uses Valid bit to qualify MATCH output
• High-Speed Address-to-Match comparison times
– 8/9/10/12ns over commercial temperature range
BRDY circuitry included inside the Cache-Tag for highest
speed operation
• Asynchronous Read/Match operation with Synchronous
Write and Reset operation
• Separate WE for the TAG bits and the Status bits
• Separate OE for the TAG bits, the Status bits, and BRDY
• Synchronous RESET pin for invalidation of all Tag entries
• Dual Chip selects for easy depth expansion with no
performance degredation
• I/O pins both 5V TTL and 3.3V LVTTL compatible with
VCCQ pins
PWRDN pin to place device in low-power mode
• Packaged in a 80-pin Thin Plastic Quad Flat Pack
(TQFP)
DESCRIPTION:
The IDT71215 is a 245,760-bit Cache Tag StaticRAM,
organized 16K x 15 and designed to support the Pentium and
other Intel processors at bus speeds up to 66MHz. There are
twelve common I/O TAG bits, with the remaining three bits
used as status bits. A 12-bit comparator is on-chip to allow fast
comparison of the twelve stored TAG bits and the current Tag
input data. An active HIGH MATCH output is generated when
these two groups of data are the same for a given address.
This high-speed MATCH signal, with tADM as fast as 8ns,
provides the fastest possible enabling of secondary cache
accesses.
The three separate I/O status bits (VLD, DTY, and WT) can
be configured for either dedicated or generic functionality,
depending on the SFUNC input pin. With SFUNC LOW, the
status bits are defined and used internally by the device,
allowing easier determination of the validity and use of the
given Tag data. SFUNC HIGH releases the defined internal
status bit usage and control, allowing the user to configure the
status bit information to fit his system needs. A synchronous
RESET pin, when held LOW at a rising clock edge, will reset
all status bits in the array for easy invalidation of all Tag
addresses.
The IDT71215 also provides the option for Burst Ready
(BRDY) generation within the cache tag itself, based upon
MATCH, VLD bit, WT bit, and external inputs provided by the
user. This can significantly simplify cache controller logic and
minimize cache decision time. Match and Read operations
are both asynchronous in order to provide the fastest access
times possible, while Write operations are synchronous for
ease of system timing.
The IDT71215 uses a 5V power supply on Vcc with sepa-
rate VCCQ pins provided for the outputs to offer compliance
with both 5.0V TTL and 3.3V LVTTL Logic levels. The PWRDN
pin offers a low-power standby mode to reduce power con-
sumption by 90%, providing significant system power sav-
ings.
The IDT71215 is fabricated using IDT's high-performance,
high-reliability BiCMOS technology and is offered in a space-
saving 80-pin Thin Plastic Quad Flat Pack (TQFP) package.
PIN DESCRIPTIONS
A0 – A13
CS1, CS2
WET
WES
OET
OES
RESET
PWRDN
SFUNC
W/R
VLDIN / S1IN
DTYIN / S2IN
WTIN / S3IN
Address Inputs
Chip Selects
Write Enable - Tag Bits
Write Enable - Status Bits
Output Enable - Tag Bits
Output Enable - Status Bits
Status Bit Reset
Powerdown Mode Control Pin
Status Bit Function Control Pin
Write/Read Input from Processor
Valid Bit / S1 Bit Input
Dirty Bit / S2 Bit Input
Write Through Bit / S3 Bit Input
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Pentium is a trademark of Intel Corporation
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
CLK
BRDYH
BRDYOE
BRDYIN
BRDY
TAG0 – TAG11
VLDOUT / S1OUT
DTYOUT / S2OUT
WTOUT / S3OUT
MATCH
VCC
VCCQ
VSS
System Clock
BRDY Force High
BRDY Output Enable
Additional BRDY Input
Burst Ready
Tag Data Input/Outputs
Valid Bit / S1 Bit Output
Dirty Bit / S2 Bit Output
Write Through Bit / S3 Bit Output
Match
+5V Power
Output Buffer Power
Ground
Input
Input
Input
Input
Output
I/O
Output
Output
Output
Output
Pwr
QPwr
Gnd
3075 tbl 01
AUGUST 1996
14.3
DSC-3075/3
1

1 page




IDT71215S8PF pdf
IDT71215
BiCMOS 16Kx15 CACHE-TAG RAM
TRUTH TABLES (CONT.)
COMMERCIAL TEMPERATURE RANGE
MATCH FUNCTION(1, 2, 3)
CS1 CS2 SFUNC OET WET WES
TAG VLD(4) DTY(4) WT(4) MATCH
OPERATION
HX X X XX
Hi-Z –
– – Hi-Z
Deselected
XL X X XX
Hi-Z –
– – Hi-Z
Deselected
LH X X XX
– – – – DOUT
Selected
LH X L HX
DOUT
––
L
Read Tag I/O
LH X H LX
DIN
––
L
Write Tag I/O
LH X X XL
– DIN DIN DIN L
Write Status Bits
LH L H HH
TAGIN L
––
L
Invalid Data - Dedicated Status Bits
LH L H HH
TAGIN H
––
M
Match - Dedicated Status Bits
LH H H HH
TAGIN X
––
M
Match - Generic Status Bits
NOTES:
1. "H" = VIH, "L" = VIL, "X" = don't care, "–" = unrelated.
2. M = HIGH if TAGIN equals the memory contents at that address; M = LOW if TAGIN does not equal the memory contents at that address.
3. PWRDN and RESET are HIGH for this table. W/R, BRDYH, ,BRDYOE ,BRDYIN OES, and CLK are "X".
4. This column represents the stored memory cell data for the given Status bit at the selected address.
3075 tbl 04
BRDY FUNCTION(1, 2, 3, 5)
BRDYOE BRDYIN(6) OET WET WES BRDYH W/R SFUNC VLD(4) DTY(4) WT(4) TAG MATCH BRDY
OPERATION
H
X X XX X X X
X–X–
– Hi-Z BRDY Disabled
L
L X XX X X X
X – X – X L Ext BRDY Input (7)
L
H L XX X X X
X – X DOUT L
H
Read TAG
L
H X LX X X X
X – X DIN
L
H
Write TAG
L
H XXL
X XX
DIN DIN DIN
L
H
Write Status
L
H X XX H X X
X – X – X H Force BRDY HIGH
L
H X XX X X L
L–X– L H
Invalid TAG
L
H X XX X H L
X–H– X H
Write Through
L
H H HH L X L
H – L TAGIN M
M
Compare
L
H H HH L L L
H – X TAGIN M
M
Compare
L
H H HH L X L
H – X TAGIN M
M
Compare
L
H H HH L X H
X – X TAGIN M
M
Compare
NOTES:
3075 tbl 05
1. "H" = VIH, "L" = VIL, "X" = don't care, "–" = unrelated.
2. M = HIGH if TAGIN equals the memory contents at that address; M = LOW if TAGIN does not equal the memory contents at that address.
3. PWRDN and RESET are HIGH for this table. CLK and OES are "X".
4. This column represents the stored memory cell data for the given Status bit at the selected address.
5. CS1 is LOW, CS2 is HIGH for this table.
6. BRDYIN is a synchronous input; thus the inputs noted in the table must be applied during a rising CLK edge.
7. BRDYIN will be a factor in determining the BRDY output in all cases except when BRDYH is HIGH and there is a valid MATCH. In that case, BRDY will
be LOW(Valid).
14.3 5

5 Page





IDT71215S8PF arduino
IDT71215
BiCMOS 16Kx15 CACHE-TAG RAM
TIMING WAVEFORMS OF WRITE AND READ CYCLES
COMMERCIAL TEMPERATURE RANGE
14.3 11

11 Page







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