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PDF IDT71028S70 Data sheet ( Hoja de datos )
| Número de pieza | IDT71028S70 | |
| Descripción | CMOS STATIC RAM 1 MEG (256K x 4-BIT) | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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Integrated Device Technology, Inc.
CMOS STATIC RAM
1 MEG (256K x 4-BIT)
IDT71028S70
FEATURES:
• 256K x 4 CMOS static RAM
• Equal access and cycle times
— Commercial: 70ns
• One Chip Select plus one Output Enable pin
• Bidirectional data Inputs and outputs directly
TTL-compatible
• Low power consumption via chip deselect
• Available in 400 mil Plastic SOJ package
DESCRIPTION:
The IDT71028 is a 1,024,576-bit medium-speed static
RAM organized as 256K x 4. It is fabricated using IDT’s high-
perfomance, high-reliability CMOS technology. This state-of-
the-art technology, combined with innovative circuit design
techniques, provides a cost-effective solution for your memory
needs.
The IDT71028 has an output enable pin which operates as
fast as 30ns, with address access times as fast as 70ns. All
bidirectional inputs and outputs of the IDT71028 are TTL-
compatible and operation is from a single 5V supply. Fully
static asynchronous circuitry is used, requiring no clocks or
refresh for operation.
The IDT71028 is packaged in 28-pin 400 mil Plastic SOJ
package.
FUNCTIONAL BLOCK DIAGRAM
A0
ADDRESS
DECODER
1,048,576-BIT
MEMORY
ARRAY
A17
4
I/O0 – I/O3
4
I/O CONTROL
CS CONTROL
WE LOGIC
OE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
3569 drw 01
MAY 1996
3569/-
1
1 page  
IDT71028S70
CMOS STATIC RAM 1 MEG (256K x 4-BIT)
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
ADDRESS
OE
CS
DATAOUT
VCC SUPPLY ICC
CURRENT ISB
tRC
tAA
tOE
tOLZ (5)
tCLZ (5)
tACS (3)
HIGH IMPEDANCE
tPU
COMMERCIAL TEMPERATURE RANGE
tOHZ (5)
tCHZ (5)
DATAOUT VALID
tPD
3569 drw 05
TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)
ADDRESS
DATAOUT
tRC
tOH
PREVIOUS DATAOUT VALID
tAA
tOH
DATAOUT VALID
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
3569 drw 6
5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet IDT71028S70.PDF ] | |
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