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PDF IDT71016 Data sheet ( Hoja de datos )
| Número de pieza | IDT71016 | |
| Descripción | CMOS Static RAM 1 Meg (64K x 16-Bit) | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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CMOS Static RAM
1 Meg (64K x 16-Bit)
IDT71016
Features
◆ 64K x 16 advanced high-speed CMOS Static RAM
◆ Equal access and cycle times
– Commercial and Industrial: 12/15/20ns
◆ One Chip Select plus one Output Enable pin
◆ Bidirectional data inputs and outputs directly TTL-
compatible
◆ Low power consumption via chip deselect
◆ Upper and Lower Byte Enable Pins
◆ Commercial and industrial product available in 44-pin
Plastic SOJ package and 44-pin TSOP package
Functional Block Diagram
Output
OE Enable
Buffer
Description
The IDT71016 is a 1,048,576-bit high-speed Static RAM organized
as 64K x 16. It is fabricated using IDT’s high-perfomance, high-reliability
CMOS technology. This state-of-the-art technology, combined with
innovative circuit design techniques, provides a cost-effective solution for
high-speed memory needs.
The IDT71016 has an output enable pin which operates as fast as 7ns,
with address access times as fast as 12ns. All bidirectional inputs and
outputs of the IDT71016 are TTL-compatible and operation is from a single
5Vsupply. Fullystaticasynchronouscircuitryisused,requiringnoclocks
or refresh for operation.
The IDT71016 is packaged in a JEDEC standard 44-pin Plastic SOJ
and 44-pin TSOP Type II.
A0 - A15
Address
Buffers
Chip
CS Enable
Buffer
Write
WE Enable
Buffer
BHE
BLE
Byte
Enable
Buffers
©2004 Integrated Device Technology, Inc.
Row / Column
Decoders
64K x 16
Memory
Array
8
Sense
16 Amps
and
Write
Drivers
8
High
Byte
I/O
Buffer
Low
Byte
I/O
Buffer
,I/O 15
8
I/O 8
I/O 7
8
I/O 0
3210 drw 01
JANUARY 2004
1
DSC-3210/8
1 page  
IDT71016, CMOS Static RAM
1 Meg (64K x 16-bit)
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics (VCC = 5.0V ± 10%, Commercial and Industrial Range)
71016S12
71016S15
71016S20
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC Read Cycle Time
12 ____ 15 ____ 20 ____ ns
tAA Address Access Time
____ 12 ____ 15 ____ 20 ns
tACS Chip Select Access Time
____ 12 ____ 15 ____ 20 ns
tCLZ (1 )
Chip Select Low to Output in Low-Z
4 ____ 5 ____ 5 ____ ns
tCHZ(1)
Chip Select High to Output in High-Z
____ 6 ____ 6 ____ 8 ns
tOE Output Enable Low to Output Valid
____ 7 ____ 8 ____ 10 ns
tOLZ(1)
Output Enable Low to Output in Low-Z
0 ____ 0 ____ 0 ____ ns
tOHZ(1)
Output Enable High to Output in High-Z
____ 6 ____ 6 ____ 8 ns
tOH Output Hold from Address Change
4 ____ 4 ____ 5 ____ ns
tBE Byte Enable Low to Output Valid
____ 7 ____ 8 ____ 10 ns
tBLZ(1)
Byte Enable Low to Output in Low-Z
0 ____ 0 ____ 0 ____ ns
tBHZ(1)
Byte Enable High to Output in High-Z
____ 6 ____ 6 ____ 8 ns
WRITE CYCLE
tWC Write Cycle Time
12 ____ 15 ____ 20 ____ ns
tAW Address Valid to End of Write
9 ____ 10 ____ 12 ____ ns
tCW Chip Select Low to End of Write
9 ____ 10 ____ 12 ____ ns
tBW Byte Enable Low to End of Write
9 ____ 10 ____ 12 ____ ns
tAS Address Set-up Time
0 ____ 0 ____ 0 ____ ns
tWR Address Hold from End of Write
0 ____ 0 ____ 0 ____ ns
tWP Write Pulse Width
9 ____ 10 ____ 12 ____ ns
tDW Data Valid to End of Write
7 ____ 8 ____ 10 ____ ns
tDH Data Hold Time
0 ____ 0 ____ 0 ____ ns
tOW(1)
Write Enable High to Output in Low-Z
1 ____
1 ____
1 ____ ns
tWHZ(1)
Write Enable Low to Output in High-Z
____ 6 ____ 6 ____ 8 ns
NOTE:
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
3210 tbl 10
Timing Waveform of Read Cycle No. 1(1,2,3)
ADDRESS
tRC
DATAOUT
tOH
PREVIOUS DATAOUT VALID
tAA
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. OE, BHE, and BLE are LOW.
6.452
tOH
DATAOUT VALID
,3210 drw 06
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet IDT71016.PDF ] | |
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