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PDF IDT70V9279S Data sheet ( Hoja de datos )
| Número de pieza | IDT70V9279S | |
| Descripción | HIGH-SPEED 3.3V 32K x 16 SYNCHRONOUS DUAL-PORT STATIC RAM | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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HIGH-SPEED 3.3V 32K x 16
SYNCHRONOUS
DUAL-PORT STATIC RAM
IDT70V9279S/L
Features:
x True Dual-Ported memory cells which allow simultaneous
access of the same memory location
x High-speed clock to data access
– Commercial: 9/12/15ns (max.)
x Low-power operation
– IDT70V9279S
Active: 429mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V9279L
Active: 429mW (typ.)
Standby: 1.32mW (typ.)
x Flow-through or Pipelined output mode on either port via
the FT/PIPE pin
x Counter enable and reset features
x Dual chip enables allow for depth expansion without
additional logic
x Full synchronous operation on both ports
– 4ns setup to clock and 1ns hold on all control, data,
and address inputs
– Data input, address, and control registers
– Fast 9ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 15ns cycle time, 66MHz operation in Pipelined output mode
x Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
x LVTTL- compatible, single 3.3V (±0.3V) power supply
x Industrial temperature range (–40°C to +85°C) is
available for selected speeds
x Available in a 128-pin Thin Quad Flatpack (TQFP) package
Functional Block Diagram
R/WL
UBL
CE0L
CE1L
LBL
OEL
1
0
0/1
R/WR
UBR
CE0R
1
0
CE1R
0/1
LBR
OER
FT/PIPEL
I/O8L-I/O15L
I/O0L-I/O7L
0/1 1b 0bb a 1a 0a
A14L
A0L
CLKL
ADSL
CNTENL
CNTRSTL
Counter/
Address
Reg.
I/O
Control
I/O
Control
MEMORY
ARRAY
0a 1a
a
b0b 1b
0/1
Counter/
Address
Reg.
FT/PIPER
,
I/O8R-I/O15R
I/O0R-I/O7R
A14R
A0R
CLKR
ADSR
CNTENR
CNTRSTR
3743 drw 01
©2000 Integrated Device Technology, Inc.
1
JANUARY 2001
DSC 3743/6
1 page  
IDT70V9279S/L
High-Speed 32K x 16 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 3.3V ± 0.3V)
70V9279S
70V9279L
Symbol
Parameter
Test Conditions
Min. Max. Min. Max. Unit
|ILI| Input Leakage Current(1)
VCC = 3.6V, VIN = 0V to VCC
___ 10 ___
5 µA
|ILO| Output Leakage Current
CE = VIH or CE1 = VIL, VOUT = 0V to VCC
___ 10 ___
5 µA
VOL Output Low Voltage
IOL = +4mA
___ 0.4 ___ 0.4 V
VOH Output High Voltage
IOH = -4mA
2.4 ___ 2.4 ___ V
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
3743 tbl 08
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range(3,6,7) (VCC = 3.3V ± 0.3V)
70V9279X9
Com'l Only
70V9279X12
Com'l Only
70V9279X15
Com'l Only
Symbol
Parameter
Test Condition
Version Typ.(4) Max. Typ.(4) Max. Typ.(4) Max. Unit
ICC Dynamic
Operating
Current (Both
Ports Active)
CEL and CER= VIL,
Outputs Disabled,
f = fMAX(1)
COM'L S 180 260 150 240 130 220 mA
L 180 225 150 205 130 185
IND S ____ ____ ____ ____ ____ ____
L ____ ____ ____ ____ ____ ____
ISB1 Standby
Current (Both
Ports - TTL
Level Inputs)
CEL = CER = VIH
f = fMAX(1)
COM'L S 50 75 40 65 30 55 mA
L 50 65 40 50 30 35
IND S ____ ____ ____ ____ ____ ____
L ____ ____ ____ ____ ____ ____
ISB2 Standby
Current (One
Port - TTL
Level Inputs)
CE"A" = VIL and
CE"B" = VIH(5)
COM'L S 110 170 100 160 90 150 mA
L 110 150 100 140 90 130
Active Port Outputs Disabled,
f=fMAX(1)
IND S ____ ____ ____ ____ ____ ____
L ____ ____ ____ ____ ____ ____
ISB3 Full Standby
Current (Both
Ports - CMOS
Level Inputs)
Both Ports CEL and
CER > VCC - 0.2V,
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(2)
COM'L S 1.0 5 1.0 5 1.0 5 mA
L 0.4 3 0.4 3 0.4 3
IND S ____ ____ ____ ____ ____ ____
L ____ ____ ____ ____ ____ ____
ISB4 Full Standby
Current (One
Port - CMOS
Level Inputs)
CE"A" < 0.2V and
COM'L S 100
160
90
150
80
140 mA
CE"B" > VCC - 0.2V(5)
L 100
140
90
130
80
120
VIN > VCC - 0.2V or
VIN < 0.2V, Active Port,
IND
S ____
____
____
____
____
____
Outputs Disabled , f = fMAX(1)
L ____ ____ ____ ____ ____ ____
3743 tbl 09
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. Vcc = 3.3V, TA = 25°C for Typ, and are not production tested. ICC DC(f=0) = 90mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V
CEX > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V
'X' represents "L" for left port or "R" for right port.
6. 'X' in part numbers indicate power rating (S or L).
7. Industrial temperature: for specific speeds, packages and powers contact your sales office.
6.452
5 Page 
IDT70V9279S/L
High-Speed 32K x 16 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3)
tCYC2
tCH2
tCL2
CLK
CE0
CE1
UB, LB
R/W
ADDRESS(4)
DATAIN
DATAOUT
tSC tHC
tSB tHB
tSW tHW
An
tSA tHA
An +1
tCD2
(2)
READ
tSW tHW
An + 2
An + 2
tSD tHD
An + 3
Dn + 2
tCKHZ (1)
Qn
NOP (5)
WRITE
An + 4
tCKLZ(1)
tCD2
Qn + 3
READ
3743 drw 10
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(3)
tCYC2
tCH2
tCL2
CLK
CE0
CE1
UB, LB
R/W
tSC tHC
tSB tHB
tSW tHW
tSW tHW
(4)
ADDRESS
DATAIN
DATAOUT
An
tSA tHA
(2)
An +1
An + 2
tSD tHD
tCD2
Dn + 2
Qn
tOHZ(1)
An + 3
Dn + 3
An + 4
An + 5
tCKLZ(1)
tCD2
Qn + 4
OE
READ
WRITE
READ
3743 drw 11
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.1412
11 Page | ||
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| PDF Descargar | [ Datasheet IDT70V9279S.PDF ] | |
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