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PDF IDT70V7519S Data sheet ( Hoja de datos )
| Número de pieza | IDT70V7519S | |
| Descripción | HIGH-SPEED 3.3V 256K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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HIGH-SPEED 3.3V 256K x 36
SYNCHRONOUS
BANK-SWITCHABLE
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
IDT70V7519S
Features:
x 256K x 36 Synchronous Bank-Switchable Dual-ported
SRAM Architecture
– 64 independent 4K x 36 banks
– 9 megabits of memory on chip
x Bank access controlled via bank address pins
x High-speed data access
– Commercial: 3.4ns(200MHz)/3.6ns (166MHz)/4.2ns
(133MHz) (max.)
– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
x Selectable Pipelined or Flow-Through output mode
x Counter enable and repeat features
x Dual chip enables allow for depth expansion without
additional logic
x Full synchronous operation on both ports
– 5ns cycle time, 200MHz operation (14Gbps bandwidth)
– Fast 3.4ns clock to data out
– 1.5ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 200MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
x Separate byte controls for multiplexed bus and bus
matching compatibility
x LVTTL- compatible, 3.3V (±150mV) power supply
for core
x LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
x Industrial temperature range (-40°C to +85°C) is
available at 166MHz and 133MHz
x Available in a 208-pin Plastic Quad Flatpack (PQFP),
208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball
Grid Array (BGA)
x Supports JTAG features compliant with IEEE 1149.1
Functional Block Diagram
PL/FTL
OPTL
CLKL
ADSL
CNTENL
REPEATL
R/WL
CE0L
CE1L
BE3L
BE2L
BE1L
BE0L
OEL
CONTROL
LOGIC
I/O0L-35L
I/O
CONTROL
A11L
A0L
BA5L
BA4L
BA3L
BA2L
BA1L
BA0L
ADDRESS
DECODE
BANK
DECODE
NOTE:
1. The Bank-Switchable dual-port uses a true SRAM
core instead of the traditional dual-port SRAM core.
As a result, it has unique operating characteristics.
Please refer to the functional description on page 19
for details.
©2002 Integrated Device Technology, Inc.
MUX
4Kx36
MEMORY
ARRAY
(BANK 0)
MUX
MUX
4Kx36
MEMORY
ARRAY
(BANK 1)
MUX
TDI
TDO
MUX
4Kx36
MEMORY
ARRAY
(BANK 63)
MUX
JTAG
TMS
TCK
TRST
1
CONTROL
LOGIC
I/O
CONTROL
PL/FTR
OPTR
CLKR
ADSR
CNTENR
REPEATR
R/WR
CE0R
CE1R
BE3R
BE2R
BE1R
BE0R
OER
I/O0R-35R
ADDRESS
DECODE
BANK
DECODE
A11R
A0R
BA5R
BA4R
BA3R
BA2R
BA1R
BA0R
5618 drw 01
,
DECEMBER 2002
DSC 5618/5
1 page  
IDT70V7519S
High-Speed 256K x 36 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
Right Port
Names
CE0L, CE1L
R/WL
CE0R, CE1R
R/WR
Chip Enables
Read/Write Enable
OEL
BA0L - BA5L
OER
BA0R - BA5R
Output Enable
Bank Address(4)
A0L - A11L
A0R - A11R
Address
I/O0L - I/O35L
I/O0R - I/O35R
Data Input/Output
CLKL
PL/FTL
CLKR
PL/FTR
Clock
Pipeline/Flow-Through
ADSL
ADSR
Address Strobe Enable
CNTENL
REPEATL
BE0L - BE3L
VDDQL
OPTL
CNTENR
REPEATR
BE0R - BE3R
VDDQR
OPTR
VDD
VSS
TDI
TDO
TCK
TMS
TRST
Counter Enable
Counter Repeat(3)
Byte Enables (9-bit bytes)
Power (I/O Bus) (3.3V or 2.5V)(1)
Option for selecting VDDQX(1,2)
Power (3.3V)(1)
Ground (0V)
Test Data Input
Test Data Output
Test Logic Clock (10MHz)
Test Mode Select
Reset (Initialize TAP Controller)
5618 tbl 01
NOTES:
1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
2. OPTX selects the operating voltage levels for the I/Os and controls on that port.
If OPTX is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V
levels and VDDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that
port's I/Os and address controls will operate at 2.5V levels and VDDQX must be
supplied at 2.5V. The OPT pins are independent of one another—both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.
3. When REPEATX is asserted, the counter will reset to the last valid address loaded
via ADSX.
4. Accesses by the ports into specific banks are controlled by the bank address
pins under the user's direct control: each port can access any bank of memory
with the shared array that is not currently being accessed by the opposite port
(i.e., BA0L - BA5L ≠ BA0R - BA5R). In the event that both ports try to access the
same bank at the same time, neither access will be valid, and data at the two
specific addresses targeted by the ports within that bank may be corrupted (in
the case that either or both ports are writing) or may result in invalid output (in
the case that both ports are trying to read).
6.452
5 Page 
IDT70V7519S
High-Speed 256K x 36 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(2,3) (VDD = 3.3V ± 150mV, TA = 0°C to +70°C)
70V 7519S 200 (5)
Com'l Only
70V 7519S 166 (3,4 )
C o m 'l
& Ind
70V 7519S 133(3)
C o m 'l
& Ind
Symbol
tCY C1
tCY C2
tC H 1
tCL 1
tC H 2
tCL 2
tR
tF
Clo ck Cycle Time (Flo w-Thro ug h)(1)
Clo ck Cycle Time (P ip e line d)(1)
Clo ck Hig h Time (Flo w-Thro ug h)(1)
Clo ck Lo w Tim e (Flow-Thro ugh)(1)
Clo ck Hig h Time (P ip e line d)(2)
Clo ck Lo w Tim e (P ipe line d )(1)
Clock Rise Time
Clock Fall Time
P aram eter
Min. Max. Min. Max. Min. Max. Unit
15 ____ 20 ____ 25 ____ ns
5 ____ 6 ____ 7.5 ____ ns
5 ____ 6 ____ 7 ____ ns
5 ____ 6 ____ 7 ____ ns
2.0 ____ 2.1 ____ 2.6 ____ ns
2.0 ____ 2.1 ____ 2.6 ____ ns
____ 1.5 ____ 1.5 ____ 1.5 ns
____ 1.5 ____ 1.5 ____ 1.5 ns
tSA Ad dre ss Se tup Tim e
tHA Ad dre ss Ho ld Tim e
tS C Chip E nab le S e tup Time
tHC Chip Enab le Ho ld Time
tS W R/W S e tup Time
tHW R/W Ho ld Time
tS D Inp ut Data S e tup Time
tHD Input Data Ho ld Tim e
tSA D ADS S e tup Time
tHA D ADS Ho ld Time
tSCN CNTEN S e tup Time
tHCN CNTEN Ho ld Time
tS RP T REPEAT S e tup Time
tHRP T REPEAT Ho ld Time
tOE Outp ut Enab le to Data Valid
tOLZ Outp ut Enab le to Outp ut Lo w-Z
1.5 ____ 1.7 ____ 1.8 ____ ns
0.5 ____ 0.5 ____ 0.5 ____ ns
1.5 ____ 1.7 ____ 1.8 ____ ns
0.5 ____ 0.5 ____ 0.5 ____ ns
1.5 ____ 1.7 ____ 1.8 ____ ns
0.5 ____ 0.5 ____ 0.5 ____ ns
1.5 ____ 1.7 ____ 1.8 ____ ns
0.5 ____ 0.5 ____ 0.5 ____ ns
1.5 ____ 1.7 ____ 1.8 ____ ns
0.5 ____ 0.5 ____ 0.5 ____ ns
1.5 ____ 1.7 ____ 1.8 ____ ns
0.5 ____ 0.5 ____ 0.5 ____ ns
1.5 ____ 1.7 ____ 1.8 ____ ns
0.5 ____ 0.5 ____ 0.5 ____ ns
____ 4.0 ____ 4.0 ____ 4.2 ns
0.5 ____ 0.5 ____ 0.5 ____ ns
tO HZ Outp ut Enab le to Outp ut Hig h-Z
tCD1 Clo ck to Data Valid (Flo w-Thro ug h)(1)
tCD2 Clo ck to Data Valid (Pip e lined )(1)
tDC Data Output Ho ld A fte r Clo ck Hig h
1 3.4
1 3.6
1 4.2 ns
____ 10 ____ 12 ____ 15 ns
____ 3.4 ____ 3.6 ____ 4.2 ns
1 ____
1 ____
1 ____ ns
tCK HZ Clo ck Hig h to Outp ut Hig h-Z
tCKLZ Clo ck Hig h to Outp ut Lo w-Z
1 3.4
1 3.6
1 4.2 ns
0.5 ____ 0.5 ____ 0.5 ____ ns
Port-to-Port Delay
tCO Clo ck-to -Clo ck Offse t
5.0 ____ 6.0 ____ 7.5 ____ ns
NOTES:
5 618 tb l 11
1. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPEX = VIH. Flow-through parameters (tCYC1, tCD1) apply when
FT/PIPEX = VIL for that port.
2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPE. FT/PIPE should be treated as a
DC signal, i.e. steady state during operation.
3. These values are valid for either level of VDDQ (3.3V/2.5V). See page 5 for details on selecting the desired operating voltage levels for each port.
4. 166MHz Industrial Temperature not available in BF-208 package.
5. This speed grade available when VDDQ = 3.3.V for a specific port (i.e., OPTx = VIH). This speed grade available in BC-256 package only.
6.1412
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| PDF Descargar | [ Datasheet IDT70V7519S.PDF ] | |
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