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PDF IDT70V08 Data sheet ( Hoja de datos )
| Número de pieza | IDT70V08 | |
| Descripción | HIGH-SPEED 64K x 8 DUAL-PORT STATIC RAM | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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HIGH-SPEED
64K x 8 DUAL-PORT
STATIC RAM
IDT70V08S/L
Features
x True Dual-Ported memory cells which allow simultaneous
access of the same memory location
x High-speed access
– Commercial: 15/20/25/35ns (max.)
x Low-power operation
– IDT70V08S
Active: 550mW (typ.)
Standby: 5mW (typ.)
– IDT70V08L
Active: 550mW (typ.)
Standby: 1mW (typ.)
x Dual chip enables allow for depth expansion without
external logic
x IDT70V08 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading more
than one device
x M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
x Busy and Interrupt Flags
x On-chip port arbitration logic
x Full on-chip hardware support of semaphore signaling
between ports
x Fully asynchronous operation from either port
x LVTTL-compatible, single 3.3V (±0.3V) power supply
x Available in a 100-pin TQFP
x Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Functional Block Diagram
R/W L
CE0L
CE1L
OEL
R/WR
CE0R
CE1R
OE R
I/O 0-7L
I/O
Control
I/O
Control
BUSY
(1,2)
L
A15L
A0L
Address
Decoder
64Kx8
MEMORY
ARRAY
70V08
A15L
A 0L
CE 0L
CE1L
OE L
R/W L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
SEM L
INT
(2)
L
M/S(1)
NOTES:
1. BUSY is an input as a Slave (M/S-VIL) and an output when it is a Master (M/S-VIH).
2. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
©2000 Integrated Device Technology, Inc.
1
I/O 0-7R
BUSY
(1,2)
R
Address
Decoder
A15R
A 0R
A15R
A 0R
CE0R
CE1R
OER
R/WR
3740 drw 01
SEMR
INT R (2)
JANUARY 2001
DSC-3740/4
1 page  
IDT70V08S/L
High-Speed 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 3.3V ± 0.3V)
70V08S
70V08L
Symbol
Parameter
Test Conditions
Min. Max. Min. Max. Unit
|ILI| Input Leakage Current(1)
VCC = 3.6V, VIN = 0V to VCC
___ 10 ___
5 µA
|ILO| Output Leakage Current
CE(2) = VIH, VOUT = 0V to VCC
___ 10 ___
5 µA
VOL Output Low Voltage
IOL = +4mA
___ 0.4 ___ 0.4 V
VOH Output High Voltage
IOH = -4mA
2.4 ___ 2.4 ___ V
NOTES:
1. At Vcc < 2.0V, input leakages are undefined.
2. Refer to Chip Enable Truth Table.
3740 tbl 09
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,6,7) (VCC = 3.3V ± 0.3V)
Symbol
Parameter
Test Condition
Version
70V08X15
Com'l Only
Typ.(2) Max
70V08X20
Com'l Only
Typ.(2) Max
Unit
ICC Dynamic Operating Current CE = VIL, Outputs Disabled
(Both Ports Active)
SEM = VIH
f = fMAX(3)
COM'L
IND
S 170 260 165 255 mA
L 170 265 165 220
S ____ ____ ____ ____
L ____ ____ ____ ____
ISB1 Standby Current
(Both Ports - TTL Level
Inputs)
CEL = CER = VIH
SEMR = SEML = VIH
f = fMAX(3)
COM'L S 44 70 39 60 mA
L 44 60 39 50
IND
S ____ ____ ____ ____
L ____ ____ ____ ____
ISB2 Standby Current
CE"A" = VIL and CE"B" = VIH(5)
(One Port - TTL Level Inputs) Active Port Outputs Disabled,
f=fMAX(3)
SEMR = SEML = VIH
COM'L
IND
S 115 160 105 155 mA
L 115 145 105 140
S ____ ____ ____ ____
L ____ ____ ____ ____
ISB3 Full Standby Current (Both Both Ports CEL and
Ports - All CMOS Level
CER > VCC - 0.2V
Inputs)
VIN > VCC - 0.2V or
VIN < 0.2V, f = 0(4)
SEMR = SEML > VCC - 0.2V
COM'L
IND
S 1.0
L 0.2
S ____
L ____
6
3
____
____
1.0 6 mA
0.2 3
____ ____
____ ____
ISB4 Full Standby Current
CE"A" < 0.2V and
(One Port - All CMOS Level CE"B" > VCC - 0.2V(5)
Inputs)
SEMR = SEML > VCC - 0.2V
VIN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Disabled
f = fMAX(3)
COM'L
IND
S 115 155 105 150 mA
L 115 140 105 135
S ____ ____ ____ ____
L ____ ____ ____ ____
NOTES:
3740 tbl 10a
1. 'X' in part numbers indicates power rating (S or L)
2. VCC = 3.3V, TA = +25°C, and are not production tested. ICCDC = 90mA (Typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions" of input levels of GND
to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6. Refer to Chip Enable Truth Table.
7. Industrial temperature: for specific speeds, packages and powers contact your sales office.
5
5 Page 
IDT70V08S/L
High-Speed 64K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
tSAA
A0-A2
VALID ADDRESS
VALID ADDRESS
SEM
I/O
R/W
tAW
tEW
tWR
tDW
DATAIN VALID
tAS tWP
tDH
tSOP
tACE
tOH
DATA OUT
VALID(2)
tSWRD
tAOE
OE
Write Cycle
Read Cycle
NOTES:
1. CE = VIH for the duration of the above timing (both write and read cycle) (Refer to Chip Enable Truth Table).
2. DATAOUT VALID represents I/O0-7 equal to semaphore value.
3740 drw 09
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
MATCH
SIDE(2) "A"
R/W"A"
SEM"A"
A0"B"-A2"B"
SIDE(2) "B"
R/W"B"
tSPS
MATCH
SEM"B"
NOTES:
1. DOR = DOL = VIL, CEL = CER = VIH (Refer to Chip Enable Truth Table).
2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied, there is no guarantee which side will be granted the semaphore flag.
3740 drw 10
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet IDT70V08.PDF ] | |
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