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PDF IDT70V05 Data sheet ( Hoja de datos )
| Número de pieza | IDT70V05 | |
| Descripción | HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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Integrated Device Technology, Inc.
HIGH-SPEED 3.3V
8K x 8 DUAL-PORT
STATIC RAM
IDT70V05S/L
FEATURES:
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• High-speed access
— Commercial: 25/35/55ns (max.)
• Low-power operation
— IDT70V05S
Active: 350mW (typ.)
Standby: 3.5mW (typ.)
— IDT70V05L
Active: 350mW (typ.)
Standby: 1mW (typ.)
• IDT70V05 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading
more than one device
• M/S = H for BUSY output flag on Master
M/S = L for BUSY input on Slave
• Busy and Interrupt Flags
FUNCTIONAL BLOCK DIAGRAM
• On-chip port arbitration logic
• Full on-chip hardware support of semaphore signaling
between ports
• Fully asynchronous operation from either port
• Devices are capable of withstanding greater than 2001V
electrostatic discharge
• Battery backup operation—2V data retention
• LVTTL-compatible, single 3.3V (±0.3V) power supply
• Available in 68-pin PGA, 68-pin PLCC, and a 64-pin
TQFP
DESCRIPTION:
The IDT70V05 is a high-speed 8K x 8 Dual-Port Static
RAM. The IDT70V05 is designed to be used as a stand-alone
Dual-Port RAM or as a combination MASTER/SLAVE Dual-
Port RAM for 16-bit-or-more word systems. Using the IDT
MASTER/SLAVE Dual-Port RAM approach in 16-bit or wider
memory system applications results in full-speed, error-free
OEL
WCEL
R/ L
OER
WCER
R/ R
I/O0L- I/O7L
BUSYL(1,2)
A12L
A0L
NOTES:
1. (MASTER):
BUSY is output;
(SLAVE): BUSY
is input.
2. BUSY outputs
and INT outputs
are non-tri-
stated push-pull.
SEML
(2)
INTL
I/O
Control
I/O
Control
Address
Decoder
CEL
OEL
WR/ L
13
MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
Address
Decoder
13
CER
WOER
R/ R
M/S
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
6.35
I/O0R-I/O7R
BUSYR(1,2)
A12R
A0R
SEMR
INTR (2)
2941 drw 01
OCTOBER 1996
DSC-2941/3
1
1 page  
IDT70V05S/L
HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE (VCC = 3.3V ± 0.3V)
IDT70V05S
IDT70V05L
Symbol
|ILI|
|ILO|
Parameter
Input Leakage Current(1)
Output Leakage Current
Test Conditions
VCC = 3.6V, VIN = 0V to VCC
CE = VIH, VOUT = 0V to VCC
Min.
—
—
Max.
10
10
Min.
—
—
Max.
5
5
VOL Output Low Voltage
IOL = 4mA
— 0.4 — 0.4
VOH Output High Voltage
IOH = -4mA
2.4 — 2.4 —
NOTE:
1. At Vcc ≤ 2.0V input leakages are undefined.
Unit
µA
µA
V
V
2941 tbl 08
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1) (VCC = 3.3V ± 0.3V)
Symbol
Parameter
Test
Condition
Version
70V05X25 70V05X35 70V05X55
Typ.(2) Max. Typ.(2) Max. Typ.(2) Max. Unit
ICC Dynamic Operating
Current
(Both Ports Active)
CE = VIL, Outputs Open
SEM = VIH
f = fMAX(3)
COM’L S 80 140 70 115 70 115 mA
L 70 120 60 100 60 100
ISB1 Standby Current
(Both Ports — TTL
Level Inputs)
CER = CEL = VIH
SEMR = SEML = VIH
f = fMAX(3)
COM’L. S 12 25 10 25 10 25 mA
L 10 20 8 20 8 20
ISB2 Standby Current
(One Port — TTL
Level Inputs)
CEL or CER = VIH
Active Port Outputs Open
f = fMAX(3)
SEMR = SEML = VIH
COM’L. S 40 82 35 72 35 72 mA
L 30 72 25 62 25 62
ISB3 Full Standby Current
(Both Ports — All
CMOS Level Inputs)
Both Ports CEL and
CER ≥ VCC - 0.2V
VIN ≥ VCC - 0.2V or
VIN ≤ 0.2V, f = 0(4)
SEMR = SEML ≥ VCC - 0.2V
COM’L. S 1.0 5 1.0 5 1.0 5 mA
L 0.2 2.5 0.2 2.5 0.2 2.5
ISB4 Full Standby Current
(One Port — All
CMOS Level Inputs)
One Port CEL or
CER ≥ VCC - 0.2V
COM’L. S 50 81 45 71 45 71 mA
L 40 71 35 61 35 61
SEMR = SEML ≥ VCC - 0.2V
VIN ≥ VCC - 0.2V or VIN ≤ 0.2V
Active Port Outputs Open
f = fMAX(3)
NOTES:
2941 tbl 09
1. "X" in part numbers indicates power rating (S or L).
2. VCC = 3.3V, TA = +25°C.
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions”
of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
6.35 5
5 Page 
IDT70V05S/L
HIGH-SPEED 3.3V 8K x 8 DUAL-PORT STATIC RAM
TIMING WAVEFORM OF SLAVE WRITE (M/S = VIL)
tWP
WR/ "A"
BUSY"B"
tWB( 3 )
WR/ "B"
(2)
COMMERCIAL TEMPERATURE RANGE
tWH ( 1 )
2941 drw 14
WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE TIMING (M/S = VIH)(1)
ADDR"A"
and "B"
ADDRESSES MATCH
CE"A"
CE"B"
BUSY"B"
tAPS (2)
tBAC
tBDC
2941 drw 15
WAVEFORM OF BUSY ARBITRATION CYCLE CONTROLLED BY ADDRESS MATCH TIMING
(M/S = VIH)(1)
ADDR"A"
ADDRESS "N"
tAPS (2)
ADDR"B"
BUSY"B"
MATCHING ADDRESS "N"
tBAA
tBDA
2941 drw 16
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. If tAPS is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.
6.35 11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet IDT70V05.PDF ] | |
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