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PDF IDT70T659S Data sheet ( Hoja de datos )

Número de pieza IDT70T659S
Descripción HIGH-SPEED 2.5V 256/128K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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No Preview Available ! IDT70T659S Hoja de datos, Descripción, Manual

HIGH-SPEED 2.5V
256/128K x 36
ASYNCHRONOUS DUAL-PORT
STATIC RAM
WITH 3.3V 0R 2.5V INTERFACE
PRELIMINARY
IDT70T651/9S
Features
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 8/10/12/15ns (max.)
– Industrial: 10/12ns (max.)
RapidWrite Mode simplifies high-speed consecutive write
cycles
Dual chip enables allow for depth expansion without
external logic
IDT70T651/9 easily expands data bus width to 72 bits or
more using the Master/Slave select when cascading more
than one device
M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
Busy and Interrupt Flags
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Separate byte controls for multiplexed bus and bus
matching compatibility
Sleep Mode Inputs on both ports
Supports JTAG features compliant to IEEE 1149.1
Single 2.5V (±100mV) power supply for core
LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)
power supply for I/Os and control signals on each port
Available in a 256-ball Ball Grid Array, 208-pin Plastic Quad
Flatpack and 208-ball fine pitch Ball Grid Array.
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Functional Block Diagram
BE3L
BE2L
BE1L
BE0L
R/WL
CE0L
C E1L
BB BB BBBB
EE EE EEEE
01 23 3210
L L L L RRRR
BE 3R
BE2R
BE 1R
BE0R
R/WR
CE0R
CE1R
OEL
I/O0L- I/O35L
Dout0-8_L Dout0-8_R
Dout9-17_L Dout9-17_R
Dout18-26_L Dout18-26_R
Dout27-35_L Dout27-35_R
256/128K x 36
MEMORY
ARRAY
Di n_L
Di n_R
OER
I/O0R -I/O35R
A17L(1)
A0L
Address
Decoder
ADDR_L ADDR_R
Address
Decoder
A17R(1)
A0R
BUSYL(2,3)
SEML
INTL(3)
CE0L
CE1L
OEL
R/WL
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
M/S
OER
R/WR
CE0R
CE1R
TDI
TD O
JTAG
BUSYR(2,3)
SEMR
INTR(3)
TC K
TMS
TRST
NOTES:
ZZL(4)
ZZ
CO NT RO L
LOGIC
ZZR(4)
1. Address A17x is a NC for IDT70T659.
2. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).
3. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
4869 drw 01
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the sleep
mode pins themselves (ZZx) are not affected during sleep mode.
NOVEMBER
2003
©2003 Integrated Device Technology, Inc.
1
DSC-5632/3

1 page




IDT70T659S pdf
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Pin Configurations(1,2,3)(con't.)
Preliminary
Industrial and Commercial Temperature Ranges
03/18/03
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
A AI/O19L I/O18L VSS
TDO
NC A16L
A12L A8L BE1L VDD SEML INTL
A4L A0L OPTL I/O17L VSS
B BI/O20R VSS I/O18R TDI A17L (4) A13L
A9 L BE2L CE0L VSS BUSYL A5L A1L
VSS VDDQR I/O16L I/O15R
C CVDDQL I/O19R VDDQR VDD
NC A14 L A1 0L BE3L CE1L VSS R/WL A6L A2L
VDD I/O16R I/O15L VSS
D A DI/O22L VSS I/O21L I/O20L A15L A11L A7 L BE0L VDD OEL NC
3L VDD I/O17R VDDQ L I/O14L I/O14R
E I/O23L I/O22R VDDQR I/O21R
F VDDQL I/O23R I/O24L VSS
I/O12L I/O13R
EVSS I/O13L
FVSS I/O12R I/O11L VDDQR
G I/O26L VSS I/O25L I/O24R
H VDD I/O26R VDDQR I/O25R
J VDDQL VDD VSS ZZR
K I/O28R VSS I/O27R VS S
L I/O29R I/O28L VDDQR I/O27L
70T651/9BF
BF-208(5,6)
208-Ball
fpBGA
Top View(7)
GI/O9L VDDQL I/O10L I/O11R
HVDD I/O9R VSS I/O10R
JZZL
VDD
VSS VDDQR
KI/O7R VDDQL I/O8R VSS
LI/O6R I/O7L VSS I/O8L
M VDDQL I/O29L I/O30R VSS
N I/O31L VSS I/O31R I/O30L
MVSS I/O6L I/O5R VDDQR
NI/O3R VDDQL I/O4R I/O5L
P PI/O32R I/O32L VDDQR I/O3 5R TRST A16R
A12R
A8R BE1R
VDD SEMR
INTR A4R
I/O2L I/O3L VSS I/O4L
R RVSS I/O33L I/O34R TCK A17R(4) A13R
A9R BE2R CE0R
VSS BUSYR A5 R
A1R VSS VDDQ L I/O1R VDDQR
T TI/O33R I/O34L VDDQL TMS NC
A14R A1 0R BE3R CE1R VSS R/WR A6R
A2R VS S I/O 0R VSS I/O2R
U UVSS I/O35L VDD NC A15R A11R A7 R BE0R VDD OER M/S A3R A0R VDD OPTR I/O0L I/O1L
5632 drw 02e
NOTES:
1. All VDD pins must be connected to 2.5V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V) and 2.5V if OPT pin for that port is
set to VSS (0V).
3. All VSS pins must be connected to ground.
4. A17X is a NC for IDT70T659.
5. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
6. This package code is used to reference the package diagram.
7. This text does not indicate orientation of the actual part-marking.
5

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IDT70T659S arduino
IDT70T651/9S
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(4)
70T651/9S8(5)
Com'l Only
70T651/9S10
Com'l
& Ind(5)
Symbol
Parameter
Min. Max. Min. Max.
70T651/9S12
Com'l
& Ind
Min. Max.
70T651/9S15
Com'l Only
Min. Max.
Unit
READ CYCLE
tRC Read Cycle Time
tAA Address Access Time
tACE Chip Enable Access Time(3)
tABE Byte Enable Access Time(3)
8 ____ 10 ____ 12 ____ 15 ____ ns
____ 8 ____ 10 ____ 12 ____ 15 ns
____ 8 ____ 10 ____ 12 ____ 15 ns
____ 4 ____ 5 ____ 6 ____ 7 ns
tAOE Output Enable Access Time
tOH Output Hold from Address Change
tLZ Output Low-Z Time Chip Enable and Semaphore(1,2)
tLZOB Output Low-Z Time Output Enable and Byte Enable(1,2)
tHZ Output High-Z Time(1,2)
tPU Chip Enable to Power Up Time(2)
tPD Chip Disable to Power Down Time(2)
tSOP Semaphore Flag Update Pulse (OE or SEM)
tSAA Semaphore Address Access Time
____ 4 ____ 5 ____ 6 ____ 7 ns
3 ____ 3 ____ 3 ____ 3 ____ ns
3 ____ 3 ____ 3 ____ 3 ____ ns
0 ____ 0 ____ 0 ____ 0 ____ ns
0 3.5 0 4 0 6 0 8 ns
0 ____ 0 ____ 0 ____ 0 ____ ns
____ 7 ____ 8 ____ 8 ____ 12 ns
____ 4 ____ 4 ____ 6 ____ 8 ns
2 8 2 10 2 12 2 15 ns
tSOE Semaphore Output Enable Access Time
____ 5 ____ 5 ____ 6 ____ 7 ns
5632tbl 12
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(4)
70T651/9S8(5)
Com'l Only
70T651/9S10
Com'l
& Ind(5)
70T651/9S12
Com'l
& Ind
70T651/9S15
Com'l Only
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Unit
WRITE CYCLE
tWC Write Cycle Time
8 ____ 10 ____ 12 ____ 15 ____ ns
tEW Chip Enable to End-of-Write(3)
6 ____ 7 ____ 9 ____ 12 ____ ns
tAW Address Valid to End-of-Write
6 ____ 7 ____ 9 ____ 12 ____ ns
tAS Address Set-up Time(3)
0 ____ 0 ____ 0 ____ 0 ____ ns
tWP Write Pulse Width
6 ____ 7 ____ 9 ____ 12 ____ ns
tWR Write Recovery Time
0 ____ 0 ____ 0 ____ 0 ____ ns
tDW Data Valid to End-of-Write
4 ____ 5 ____ 7 ____ 10 ____ ns
tDH Data Hold Time
0 ____ 0 ____ 0 ____ 0 ____ ns
tWZ Write Enable to Output in High-Z(1,2)
____ 3.5 ____ 4 ____ 6 ____ 8 ns
tOW Output Active from End-of-Write(1,2)
3 ____ 3 ____ 3 ____ 3 ____ ns
tSWRD
SEM Flag Write to Read Time
4 ____ 5 ____ 5 ____ 5 ____ ns
tSPS SEM Flag Contention Window
4 ____ 5 ____ 5 ____ 5 ____ ns
NOTES:
5632 tbl 13
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 1).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE= VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. CE = VIL when
CE0 = VIL and CE1 = VIH. CE = VIH when CE0 = VIH and/or CE1 = VIL.
4. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details.
5. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only.
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