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PDF IDT70T631S Data sheet ( Hoja de datos )
| Número de pieza | IDT70T631S | |
| Descripción | HIGH-SPEED 2.5V 512/256K x 18 ASYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V 0R 2.5V INTERFACE | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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HIGH-SPEED 2.5V
512/256K x 18
ASYNCHRONOUS DUAL-PORT
STATIC RAM
WITH 3.3V 0R 2.5V INTERFACE
PRELIMINARY
IDT70T633/1S
Features
◆ True Dual-Port memory cells which allow simultaneous
access of the same memory location
◆ High-speed access
– Commercial: 8/10/12/15ns (max.)
– Industrial: 10/12ns (max.)
◆ RapidWrite Mode simplifies high-speed consecutive write
cycles
◆ Dual chip enables allow for depth expansion without
external logic
◆ IDT70T633/1 easily expands data bus width to 36 bits or
more using the Master/Slave select when cascading more
than one device
◆ M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
◆ Busy and Interrupt Flags
◆ Full hardware support of semaphore signaling between
ports on-chip
◆ On-chip port arbitration logic
◆ Fully asynchronous operation from either port
◆ Separate byte controls for multiplexed bus and bus
matching compatibility
◆ Sleep Mode Inputs on both ports
◆ Supports JTAG features compliant to IEEE 1149.1 in
BGA-208 and BGA-256 packages
◆ Single 2.5V (±100mV) power supply for core
◆ LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)
power supply for I/Os and control signals on each port
◆ Available in a 256-ball Ball Grid Array, 144-pin Thin Quad
Flatpack and 208-ball fine pitch Ball Grid Array
◆ Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Functional Block Diagram
UBL UBR
LBL LBR
R/WL
CE0 L
CE1L
BB B B
EE E E
01 1 0
LL RR
R/WR
CE0 R
CE1R
OEL
I/O0L- I/O17L
Dout0-8_L
Dout9-17_L
Dout0-8_R
Dout9-17_R
512/256K x 18
MEMORY
ARRAY
Din_L
Din_R
OER
I/O0R - I/O17R
A18L(1)
A0L
Address
Decoder
ADDR_L
ADDR_R
Address
Decoder
A18R (1)
A0R
CE0 L
CE1L
OEL
R/WL
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
OER
R/WR
CE0R
CE1R
TDI
TDO
BUSYL(2,3)
SEML
INTL(3)
M/S
NOTES:
1. Address A18x is a NC for IDT70T631.
ZZL(4)
ZZ
CONTROL
LOGIC
ZZR (4 )
2. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).
3 BUSY and INT are non-tri-state totem-pole outputs (push-pull).
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, INTx, M/S and the
sleep mode pins themselves (ZZx) are not affected during sleep mode.
©2003 Integrated Device Technology, Inc.
1
JT AG
TCK
TMS
T R ST
BUSYR(2,3)
SEMR
INTR(3)
5670 drw 01
NOVEMBER 2003
DSC-5670/3
1 page  
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Pin Configurations(1,2,3)(con't.)
Preliminary
Industrial and Commercial Temperature Ranges
03/12/03
12 3 4 56 7 8
A I/O9L
NC VSS
TDO
NC
A16L
A12L
A8L
9 10 11 12
NC VDD SEML INTL
13 14 15 16 17
AA4L A0L OPTL NC VSS
B BNC VSS NC TDI A17L A13L A9L NC CE0L VSS BUSYL A5L A1L VSS VDDQR I/O8L NC
C CVDDQL I/O9R VDDQR VDD A18L(4) A14 L
A1 0L
UBL CE1L VSS
R/WL
A6L
A2L
VDD I/O8R NC VSS
D DNC
VSS I/O10L NC
A15 L A11L
A7 L
ALBL VDD OEL NC
3L VDD
NC VDDQL I/O7L I/O7 R
E I/O11L NC VDDQR I/O10 R
EI/O6L NC VSS NC
F VDDQL I/O11R NC
VSS
FVSS I/O6R NC VDDQR
G NC VSS I/O12L NC
H VDD
NC VDDQ R I/O12R
J VDDQL VDD
VSS
ZZR
K I/O14R VSS I/O13R VSS
70T633/1BF
BF-208(5,6)
208-Ball BGA
Top View(7)
NC VDDQL I/O5L NC
G
HVDD NC VSS I/O5R
JZZL
VDD
VSS VDDQR
I/O3R VDDQL I/O4R VSS
K
L NC I/O14L VDDQR I/O13L
LNC I/O3L VSS I/O4L
M VDDQL NC I/O15R VSS
MVSS NC I/O2R VDDQR
N NC VSS NC I/O15 L
NI/O1R VDDQL NC I/O2L
P PI/O16R I/O16L VDDQR NC TRST A16R A12R A8R
NC
VDD SEMR
INTR
A4R
NC I/O1L VSS
NC
R RVSS
NC I/O17 R TCK A17R
A1 3R
A9R
NC CE0R VSS BUSYR A5R
A1R VSS VDDQ L I/O0R VDDQR
T TNC I/O17L VDDQL TMS A18R(4) A14R A1 0R UBR
CE1R VSS R/WR A6R
A2R VS S
NC
VSS NC
U UVSS
NC
VDD
NC A15R A11R
A7R LBR
VDD OER M/S
A3R
A0R VDD OPTR NC
I/ O0 L
5670 drw 02b
NOTES:
1. All VDD pins must be connected to 2.5V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is
set to VSS (0V).
3. All VSS pins must be connected to ground.
4. A18X is a NC for IDT70T631.
5. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
6. This package code is used to reference the package diagram.
7. This text does not indicate orientation of the actual part-marking.
5
5 Page 
IDT70T633/1S
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(4)
70T633/1S8(5)
Com'l Only
70T633/1S10
Com'l
& Ind(5)
Symbol
Parameter
Min. Max. Min. Max.
READ CYCLE
tRC Read Cycle Time
8 ____ 10 ____
tAA Address Access Time
____ 8 ____ 10
tACE Chip Enable Access Time(3)
____ 8 ____ 10
tABE Byte Enable Access Time(3)
4 5____ ____
tAOE Output Enable Access Time
4 5____ ____
tOH Output Hold from Address Change
3 3____ ____
tLZ Output Low-Z Time Chip Enable and Semaphore(1,2)
3 3____ ____
tLZOB Output Low-Z Time Output Enable and Byte Enable(1,2)
0 0____ ____
tHZ Output High-Z Time(1,2)
0 3.5 0
4
tPU Chip Enable to Power Up Time(2)
0 0____ ____
tPD Chip Disable to Power Down Time(2)
7 8____ ____
tSOP Semaphore Flag Update Pulse (OE or SEM)
4 4____ ____
tSAA Semaphore Address Access Time
2 8 2 10
tSOE Semaphore Output Enable Access Time
5 5____ ____
70T633/1S12
Com'l
& Ind
Min. Max.
12 ____
____ 12
____ 12
6____
6____
3 ____
3 ____
0 ____
06
0 ____
8____
6____
2 12
6____
70T633/1S15
Com'l Only
Min. Max. Unit
15 ____ ns
____ 15 ns
____ 15 ns
____ 7 ns
____ 7 ns
3 ____ ns
3 ____ ns
0 ____ ns
0 8 ns
0 ____ ns
____ 12 ns
____ 8 ns
2 15 ns
____ 7 ns
5670 tbl 12
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(4)
70T633/1S8(5)
Com'l Only
70T633/1S10
Com'l
& Ind(5)
70T633/1S12
Com'l
& Ind
70T633/1S15
Com'l Only
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Unit
WRITE CYCLE
tWC Write Cycle Time
8 ____ 10 ____ 12 ____ 15 ____ ns
tEW Chip Enable to End-of-Write(3)
6 ____ 7 ____ 9 ____ 12 ____ ns
tAW Address Valid to End-of-Write
6 ____ 7 ____ 9 ____ 12 ____ ns
tAS Address Set-up Time(3)
0 ____ 0 ____ 0 ____ 0 ____ ns
tWP Write Pulse Width
6 ____ 7 ____ 9 ____ 12 ____ ns
tWR Write Recovery Time
0 ____ 0 ____ 0 ____ 0 ____ ns
tDW Data Valid to End-of-Write
4 ____ 5 ____ 7 ____ 10 ____ ns
tDH Data Hold Time
0 ____ 0 ____ 0 ____ 0 ____ ns
tWZ Write Enable to Output in High-Z(1,2)
____ 3.5 ____ 4 ____ 6 ____ 8 ns
tOW Output Active from End-of-Write(1,2)
3 ____ 3 ____ 3 ____ 3 ____ ns
tSWRD SEM Flag Write to Read Time
4 ____ 5 ____ 5 ____ 5 ____ ns
tSPS SEM Flag Contention Window
4 ____ 5 ____ 5 ____ 5 ____ ns
NOTES:
5670 tbl 13
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 1).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE= VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. CE = VIL when
CE0 = VIL and CE1 = VIH. CE = VIH when CE0 = VIH and/or CE1 = VIL.
4. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details.
5. 8ns Commercial and 10ns Industrial speed grades are available in BF-208 and BC-256 packages only.
11
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| PDF Descargar | [ Datasheet IDT70T631S.PDF ] | |
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