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PDF IDT74FCT16601ETPF Data sheet ( Hoja de datos )

Número de pieza IDT74FCT16601ETPF
Descripción FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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No Preview Available ! IDT74FCT16601ETPF Hoja de datos, Descripción, Manual

Integrated Device Technology, Inc.
FAST CMOS
18-BIT UNIVERSAL BUS
TRANSCEIVER
WITH 3-STATE OUTPUTS
IDT74FCT16601AT/CT/ET
IDT74FCT162601AT/CT/ET
PRODUCT PREVIEW
FEATURES:
bit registered transceivers are built using advanced dual metal
• Common features:
CMOS technology. These high-speed, low-power 18-bit reg-
– 0.5 MICRON CMOS Technology
istered bus transceivers combine D-type latches and D-type
– High-speed, low-power CMOS replacement for
flip-flops to allow data flow in either direction in a transparent,
ABT functions
latched or clocked mode. Each direction has an independent
Typical tSK(o) (Output Skew) < 250ps
latch enable, an independent clock with a clock enable, and an
– Low input and output leakage 1µA (max.)
independent output enable. The package is organized with a
– ESD > 2000V per MIL-STD-883, Method 3015;
flow-through signal pin organization to ease board layout. All
> 200V using machine model (C = 200pF, R = 0)
inputs are designed with hysteresis for improved noise mar-
– Packages include 25 mil pitch SSOP, 19.6 mil pitch
gin.
WTSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack This transceiver is ideally suited for high speed memory
– Extended commercial range of -40°C to +85°C
interfaces which utilize high speed synchronous writes, by
E– VCC = 5V ±10%
clocking the data into a high speed register. Reads can then
I• Features for FCT16601AT/CT/ET:
be performed in a transparent or latched mode utilizing the
– High drive outputs (-32mA IOH, 64mA IOL)
same transceiver.
V– Power off disable outputs permit “live insertion”
The FCT16601AT/CT/ET are ideally suited for driving
– Typical VOLP (Output Ground Bounce) < 1.0V at
VCC = 5V, TA = 25°C
Ehigh-capacitance loads and low-impedance backplanes. The
output buffers are designed with power off disable capability
• Features for FCT162601AT/CT/ET:
– Balanced Output Drivers: ±24mA
– Reduced system switching noise
– Typical VOLP (Output Ground Bounce) < 0.6V at
VCC = 5V,TA = 25°C
Rto allow "live insertion" of boards when used as backplane
drivers.
The FCT162601AT/CT/ET have balanced output drive
Pwith current limiting resistors. This offers low ground bounce,
minimal undershoot, and controlled output fall times–reducing
the need for external series terminating resistors. The
DESCRIPTION:
TFCT162601AT/CT/ET are plug-in replacements for the
FCT16601AT/CT/ET and ABT16601 for on-board bus inter-
The FCT16601AT/CT/ET and FCT162601AT/CT/ET 18- face applications.
CFUNCTIONAL BLOCK DIAGRAM
OEAB 1
CLKENAB 56
CLKAB 55
U
D
2
LEAB
28
LEBA
O
R30
CLKBA
PCLKENBA 29
27
OEBA
3
A1
CE
1D
C1
CLK
CE
1D
C1
CLK
54 B1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
TO 17 OTHER CHANNELS
5.9
3247 drw 01
AUGUST 1996
DSC-3247/-
1

1 page




IDT74FCT16601ETPF pdf
IDT74FCT16601AT/CT/ET, 162601AT/CT/ET
FAST CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS
COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter
fMAX CLKAB or CLKBA frequency(4)
Condition(1)
CL = 50pF
FCT16601AT/
FCT162601AT
Min.(2)
Max.
— 150
FCT16601CT/
FCT162601CT
Min.(2)
Max.
— 150
FCT16601ET/
FCT162601ET
Min.(2)
Max.
— 150
Unit
MHz
tPLH Propagation Delay
RL = 5001.5 4.9 1.5 4.4 1.5
tPHL Ax to Bx or Bx to Ax
tPLH Propagation Delay
1.5 5.2 1.5 4.7 1.5
tPHL LEBA to Ax, LEAB to Bx
tPLH Propagation Delay
1.5 4.7 1.5 4.5 1.5
tPHL CLKBA to Ax, CLKAB to Bx
tPZH Output Enable Time
tPZL OEBA to Ax, OEAB to Bx
1.5 5.8 1.5 5.3 1.5
tPHZ Output Disable Time
tPLZ OEBA to Ax, OEAB to Bx
tSU Set-up Time, HIGH or LOW
Ax to CLKAB, Bx to CLKBA
tH Hold Time HIGH or LOW
Ax after CLKAB, Bx after CLKBA
tSU Set-up Time HIGH or LOW Clock LOW
Ax to LEAB, Bx to LEBA Clock HIGH
tH Hold Time, HIGH or LOW
Ax after LEAB, Bx after LEBA
tSU Set-up Time, CLKEN to CLK
tH Hold Time, CKLEN after CLK
tW LEAB or LEBA Pulse Width
HIGH(4)
W1.5 6.2 1.5 5.7 1.5
IE4.0 — 3.0 — 2.4
0—0—0
V1.0 — 1.0 — 1.0
E2.5 — 2.0 — 1.5
2.0 — 1.5 — 0.5
2.5 — 2.5 — 2.0
R0 — 0 — 0
P2.5 — 2.5 — 2.5
tW CLKAB or CLKBA Pulse Width
HIGH or LOW(4)
tSK(o) Output Skew(3)
NOTES:
1. See test circuits and waveforms.
T3.0 — 3.0 — 3.0
C — 0.5 — 0.5 —
U2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This parameter is guaranteed but not tested.
D
3.8 ns
4.2 ns
4.2 ns
4.8 ns
5.2 ns
— ns
— ns
— ns
— ns
— ns
— ns
— ns
— ns
— ns
0.5 ns
3247 tbl 09
O
R
P
5.9 5

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