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PDF IDT74FCT163951APV Data sheet ( Hoja de datos )

Número de pieza IDT74FCT163951APV
Descripción 3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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Integrated Device Technology, Inc.
3.3V CMOS
16-BIT REGISTERED
TRANSCEIVER
IDT74FCT163952A/B/C
FEATURES:
• 0.5 MICRON CMOS Technology
Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• Packages include 25 mil pitch SSOP, 19.6 mil pitch
TSSOP and 15.7 mil pitch TVSOP
• Extended commercial range of -40°C to +85°C
• VCC = 3.3V ±0.3V, Normal Range or
VCC = 2.7 to 3.6V, Extended Range
• CMOS power levels (0.4µW typ. static)
• Rail-to-Rail output swing for increased noise margin
• Low Ground Bounce (0.3V typ.)
• Inputs (except I/O) can be driven by 3.3V or 5V
components
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
The FCT163952A/B/C 16-bit registered transceivers are
built using advanced dual metal CMOS technology. These
high-speed, low-power devices are organized as two indepen-
dent 8-bit D-type registered transceivers with separate input
and output control for independent control of data flow in either
direction. For example, the A-to-B Enable (xCEAB) must be
LOW to enter data from the A port. xCLKAB controls the
clocking function. When xCLKAB toggles from LOW-to-HIGH,
the data present on the A port will be clocked into the register.
xOEAB performs the output enable function on the B port.
Data flow from the B port to A port is similar but requires using
xCEBA, xCLKBA, and xOEBA inputs. Full 16-bit operation is
achieved by tying the control pins of the independent trans-
ceivers together.
The FCT163952A/B/C have series current limiting resis-
tors. These offer low ground bounce, minimal undershoot, and
controlled output fall times–reducing the need for external
series terminating resistors.
1CEBA
1CLKBA
1OEAB
1CEAB
1CLKAB
1OEBA
1A1
2CEBA
2CLKBA
2OEAB
2CEAB
2CLKAB
2OEBA
C
CE 2A1
D 1B1
C
CE
D
TO 7 OTHER CHANNELS
3096 drw 01
C
CE
D
C
CE
D
2B1
TO 7 OTHER CHANNELS
3096 drw 02
The IDT Logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
8.10
AUGUST 1996
DSC-3096/4
1

1 page




IDT74FCT163951APV pdf
IDT74FCT163952/A/C
3.3V CMOS 16-BIT REGISTERED TRANSCEIVER
COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE(5)
FCT163952A
FCT163952B
FCT163952C
Symbol
Parameter
Condition(1)
Min.(2)
Max.
Min.(2)
Max.
Min.(2)
Max. Unit
tPLH Propagation Delay
CL = 50pF
2.0
10.0
2.0
7.5
2.0
6.3 ns
tPHL xCLKAB, xCLKBA to xBx, xAx RL = 500
tPZH Output Enable Time
tPZL xOEBA, xOEAB to xAx, xBx
1.5 10.5 1.5 8.0 1.5 7.0 ns
tPHZ Output Disable Time
tPLZ xOEBA, xOEAB to xAx, xBx
1.5 10.0 1.5 7.5 1.5 6.5 ns
tSU Set-up Time HIGH or LOW
2.5 — 2.5 — 2.5 — ns
xAx, xBx to xCLKAB, xCLKBA
tH Hold Time HIGH or LOW
2.0 — 1.5 — 1.5 — ns
xAx, xBx to xCLKAB, xCLKBA
tSU Set-up Time HIGH or LOW
xCEAB, xCEBA to xCLKAB,
3.0 — 3.0 — 3.0 — ns
xCLKBA
tH Hold Time HIGH or LOW
xCEAB, xCEBA to xCLKAB,
2.0 — 2.0 — 2.0 — ns
xCLKBA
tW Pulse Width HIGH or LOW
xCLKAB or xCLKBA(4)
3.0 — 3.0 — 3.0 — ns
tSK(o) Output Skew(3)
— 0.5 — 0.5 — 0.5 ns
NOTES:
3096 tbl 08
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This parameter is guaranteed but not tested.
5. Propagation Delays and Enable/Disable times are with VCC = 3.3V ±0.3V, Normal Range. For VCC = 2.7V to 3.6V, Extended Range, all Propagation Delays
and Enable/Disable times should be degraded by 20%.
8.10 5

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