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PDF IDT74FCT163601 Data sheet ( Hoja de datos )
| Número de pieza | IDT74FCT163601 | |
| Descripción | 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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®
Integrated Device Technology, Inc.
3.3V CMOS
18-BIT UNIVERSAL BUS
TRANSCEIVER
WITH 3-STATE OUTPUTS
IDT74FCT163601/A
ADVANCE INFORMATION
FEATURES:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• Packages include 25 mil pitch SSOP, 19.6 mil pitch
TSSOP and 15.7 mil pitch TVSOP
• Extended commercial range of -40°C to +85°C
• VCC = 3.3V ±0.3V, Normal Range or
VCC = 2.7 to 3.6V, Extended Range
• CMOS power levels (0.4µW typ. static)
• Rail-to-Rail output swing for increased noise margin
• Low Ground Bounce (0.3V typ.)
• Inputs (except I/O) can be driven by 3.3V or 5V
components
DESCRIPTION:
The FCT163601/A 18-bit registered transceiver is built
using advanced dual metal CMOS technology. These 18-bit
universal bus transceivers combine D-type latches and D-
type flip-flops to allow data flow in transparent, latched and
clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and clock
(CLKAB and CLKBA) inputs. The clock can be controlled by
the clock-enable (CLKENAB and CLKENBA) inputs. For A-to-
B data flow, the device operates in the transparent mode when
LEAB is high. When LEAB is low, the A data is latched if
CLKAB is held at a high or low logic level. If LEAB is low, the
A-bus data is stored in the latch/flip-flop on the low-to-high
transition of CLKAB. Output enable OEAB is active low.
When OEAB is low, the outputs are active. When OEAB is
high, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses OEBA,
LEBA, CLKBA and CLKENBA.
The FCT163601 has series current limiting resistors. These
offer low ground bounce, minimal undershoot, and controlled
output fall times-reducing the need for external series termi-
nating resistors.
FUNCTIONAL BLOCK DIAGRAM
OEAB 1
CLKENAB 56
CLKAB 55
2
LEAB
LEBA 28
30
CLKBA
CLKENBA 29
27
OEBA
3
A1
CE
1D
C1
CLK
CE
1D
C1
CLK
54 B1
TO 17 OTHER CHANNELS
3251 drw 01
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
5.9
AUGUST 1996
DSC-3251/1
1
1 page  
IDT74FCT163601/A
3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVERS
COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT163601
FCT163601A
Symbol
Parameter
Condition(1)
Min.(2)
Max.
Min.(2)
Max.
fMAX CLKAB or CLKBA frequency(4) CL = 50pF
—
100
—
150
tPLH Propagation Delay
RL = 500Ω
1.5
6.5
1.5
5.5
tPHL Ax to Bx or Bx to Ax
tPLH Propagation Delay
tPHL LEBA to Ax, LEAB to Bx
tPLH Propagation Delay
tPHL CLKBA to Ax, CLKAB to Bx
tPZH Output Enable Time
tPZL OEBA to Ax, OEAB to Bx
tPHZ Output Disable Time
tPLZ OEBA to Ax, OEAB to Bx
tSU Set-up Time, HIGH or LOW
Ax to CLKAB, Bx to CLKBA
tH Hold Time HIGH or LOW
Ax to CLKAB, Bx to CLKBA
tSU Set-up Time
Clock
HIGH or LOW
LOW
Ax to LEAB,
Clock
Bx to LEBA
HIGH
tSU Set-up Time, CLKEN to CLK
1.5 7.2 1.5 6.2
1.5 7.3 1.5 6.3
1.5 7.5 1.5 6.5
1.5 6.5 1.5 5.2
4.0 — 3.0 —
0—0—
2.5 — 2.5 —
2.0 — 2.0 —
3.0 — 2.5 —
tH Hold Time, HIGH or LOW
Ax to LEAB, Bx to LEBA
tH Hold Time, CKLEN after CLK
1.5 — 1.0 —
0—0—
tW LEAB or LEBA Pulse Width
HIGH(4)
tW CLKAB or CLKBA Pulse Width
HIGH or LOW(4)
tSK(o) Output Skew(3)
3.0 — 2.5 —
3.0 — 3.0 —
— 0.5 — 0.5
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This parameter is guaranteed but not tested.
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3251 tbl 07
5.9 5
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet IDT74FCT163601.PDF ] | |
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