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PDF IDT74FCT163543CPA Data sheet ( Hoja de datos )

Número de pieza IDT74FCT163543CPA
Descripción 3.3V CMOS 16-BIT LATCHED TRANSCEIVER
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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Integrated Device Technology, Inc.
3.3V CMOS
16-BIT LATCHED
TRANSCEIVER
IDT74FCT163543/A/C
ADVANCE INFORMATION
FEATURES:
• 0.5 MICRON CMOS Technology
Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
• Packages include 25 mil pitch SSOP, 19.6 mil pitch
TSSOP and 15.7 mil pitch TVSOP
• Extended commercial range of -40°C to +85°C
• VCC = 3.3V ±0.3V, Normal Range or
VCC = 2.7 to 3.6V, Extended Range
• CMOS power levels (0.4µW typ. static)
• Rail-to-Rail output swing for increased noise margin
• Low Ground Bounce (0.3V typ.)
• Inputs (except I/O) can be driven by 3.3V or 5V
components
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
The FCT163543/A/C 16-bit latched transceivers are built
using advanced dual metal CMOS technology. These high-
speed, low-power devices are organized as two independent 8-
bit D-type latched transceivers with separate input and output
control to permit independent control of data flow in either
direction. For example, the A-to-B Enable (xCEAB) must be
LOW in order to enter data from the A port or to output data from
the B port. xLEAB controls the latch function. When xLEAB is
LOW, the latches are transparent. A subsequent LOW-to-
HIGH transition of xLEAB signal puts the A latches in the
storage mode. xOEAB performs output enable function on the
B port. Data flow from the B port to the A port is similar but
requires using xCEBA, xLEBA, and xOEBAinputs. Flow-through
organization of signal pins simplifies layout. All inputs are
designed with hysteresis for improved noise margin.
The FCT163543/A/C have series current limiting resistors.
These offer low ground bounce, minimal undershoot, and
controlled output fall times–reducing the need for external
series terminating resistors.
1OEBA
1CEBA
1LEBA
1OEAB
1CEAB
1LEAB
1A1
2OEBA
2CEBA
2LEBA
2OEAB
2CEAB
2LEAB
C
2A1
D 1B1
C
D
TO 7 OTHER CHANNELS
3250 drw 01
C
D 2B1
C
D
TO 7 OTHER CHANNELS
3250 drw 02
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
8.7
SEPTEMBER 1996
DSC-3250/2
1

1 page




IDT74FCT163543CPA pdf
IDT74FCT163543/A/C
3.3V CMOS 16-BIT LATCHED TRANSCEIVER
COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE(4)
Symbol
Parameter
tPLH Propagation Delay
tPHL Transparent Mode
xAx to xBx or xBx to xAx
tPLH Propagation Delay
tPHL xLEBA to xAx, xLEAB to xBx
tPZH Output Enable Time
tPZL xOEBA or xOEAB to xAx or xBx
xCEBA or xCEAB to xAx or xBx
tPHZ Output Disable Time
tPLZ xOEBA or xOEAB to xAx or xBx
xCEBA or xCEAB to xAx or xBx
tSU Set-up Time HIGH or LOW
xAx or xBx to xLEAB or xLEBA
tH Hold Time HIGH or LOW
xAx or xBx to xLEAB or xLEBA
tW xLEBA or xLEAB Pulse Width
LOW
tSK(o) Output Skew(3)
Condition(1)
CL = 50pF
RL = 500
FCT163543
Min.(2)
Max.
1.5 8.5
1.5 12.5
1.5 12.0
1.5 9.0
3.0 —
2.0 —
5.0 —
— 0.5
FCT163543A
Min.(2)
Max.
1.5 6.5
1.5 8.0
1.5 9.0
1.5 7.5
2.0 —
2.0 —
5.0 —
— 0.5
FCT163543C
Min.(2)
Max.
1.5 5.3
Unit
ns
1.5 7.0 ns
1.5 8.0 ns
1.5 6.5 ns
2.0 — ns
2.0 — ns
5.0 — ns
— 0.5 ns
NOTES:
3250 tbl 07
1. See test circuits and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. Propagation Delays and Enable/Disable times are with VCC = 3.3V ±0.3V, Normal Range. For VCC = 2.7V to 3.6V, Extended Range, all Propagation Delays
and Enable/Disable times should be degraded by 20%.
8.7 5

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