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PDF IDT72V205L20PFI Data sheet ( Hoja de datos )

Número de pieza IDT72V205L20PFI
Descripción 3.3 VOLT CMOS SyncFIFO 256 x 18/ 512 x 18/ 1/024 x 18/ 2/048 x 18/ and 4/096 x 18
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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3.3 VOLT CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18,
2,048 x 18, and 4,096 x 18
IDT72V205, IDT72V215,
IDT72V225, IDT72V235,
IDT72V245
FEATURES:
256 x 18-bit organization array (IDT72V205)
512 x 18-bit organization array (IDT72V215)
1,024 x 18-bit organization array (IDT72V225)
2,048 x 18-bit organization array (IDT72V235)
4,096 x 18-bit organization array (IDT72V245)
10 ns read/write cycle time
5V input tolerant
IDT Standard or First Word Fall Through timing
Single or double register-buffered Empty and Full flags
Easily expandable in depth and width
Asynchronous or coincident Read and Write Clocks
Asynchronous or synchronous programmable Almost-Empty
and Almost-Full flags with default settings
Half-Full flag capability
Output enable puts output data bus in high-impedanc state
High-performance submicron CMOS technology
Available in a 64-lead thin quad flatpack (TQFP/STQFP)
Industrial temperature range (–40°C to +85°C) is available
DESCRIPTION:
The IDT72V205/72V215/72V225/72V235/72V245 are functionally com-
patible versions of the IDT72205LB/72215LB/72225LB/72235LB/72245LB,
designed to run off a 3.3V supply for exceptionally low power consumption.
These devices are very high-speed, low-power First-In, First-Out (FIFO)
memories with clocked read and write controls. These FIFOs are applicable
for a wide variety of data buffering needs, such as optical disk controllers, Local
Area Networks (LANs), and interprocessor communication.
TheseFIFOshave18-bitinputandoutputports. Theinputportiscontrolled
by a free-running clock (WCLK), and an input enable pin (WEN). Data is read
into the synchronous FIFO on every clock when WENis asserted. The output
port is controlled by another clock pin (RCLK) and another enable pin (REN).
The Read Clock(RCLK) can be tied to the Write Clock for single clock operation
or the two clocks can run asynchronous of one another for dual-clock operation.
An Output Enable pin (OE) is provided on the read port for three-state control
of the output.
The synchronous FIFOs have two fixed flags, Empty Flag/Output Ready
(EF/OR) and Full Flag/Input Ready (FF/IR), and two programmable flags,
Almost-Empty(PAE)andAlmost-Full(PAF). Theoffsetloadingoftheprogram-
FUNCTIONAL BLOCK DIAGRAM
WEN WCLK
FL
WXI
(HF)/WXO
RXI
RXO
RS
WRITE CONTROL
LOGIC
WRITE POINTER
EXPANSION LOGIC
RESET LOGIC
D0-D17
INPUT REGISTER
RAM ARRAY
256 x 18, 512 x 18
1,024 x 18, 2,048 x 18
4,096 x 18
OUTPUT REGISTER
OE Q0-Q17
LD
OFFSET REGISTER
FLAG
LOGIC
READ POINTER
READ CONTROL
LOGIC
FF/IR
PAF
EF/OR
PAE
HF/(WXO)
RCLK REN
4294 drw 01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
©2002 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
FEBRUARY 2002
DSC-4294/3

1 page




IDT72V205L20PFI pdf
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 3.3V ± 0.3V, TA = 0°C to +70°C; Industrial: VCC = 3.3V ± 0.3V, TA = -40°C to +85°C)
Commercial
Com'l & Ind'l(1)
IDT72V205L10
IDT72V215L10
IDT72V225L10
IDT72V235L10
IDT72V245L10
IDT72V205L15
IDT72V215L15
IDT72V225L15
IDT72V235L15
IDT72V245L15
Symbol
Parameter
Min. Max. Min. Max.
fS Clock Cycle Frequency
tA Data Access Time
— 100 — 66.7
2 6.5 2 10
tCLK Clock Cycle Time
tCLKH Clock HIGH Time
tCLKL Clock LOW Time
tDS DataSet-upTime
10 — 15 —
4.5 — 6
4.5 — 6
3 —4 —
tDH Data Hold Time
tENS EnableSet-upTime
0.5 — 1
3 —4
tENH Enable Hold Time
tRS Reset Pulse Width(2)
0.5 — 1
10 — 15 —
tRSS ResetSet-upTime
tRSR Reset Recovery Time
8
— 10
8 — 10 —
tRSF Reset to Flag and Output Time
tOLZ Output Enable to Output in Low-Z(3)
tOE Output Enable to Output Valid
tOHZ Output Enable to Output in High-Z(3)
— 15 — 15
0 —0 —
— 63 8
1 63 8
tWFF Write Clock to Full Flag
tREF Read Clock to Empty Flag
tPAFA Clock to Asynchronous Programmable Almost-Full Flag
— 6.5 — 10
— 6.5 — 10
— 17 — 20
tPAFS Write Clock to Synchronous ProgrammableAlmost-Full Flag
tPAEA Clock to Asynchronous Programmable Almost-Empty Flag
8—
17 —
10
20
tPAES Read Clock to Synchronous Programmable Almost-Empty Flag —
8—
10
tHF Clock to Half-Full Flag
— 17 — 20
tXO Clock to Expansion Out
tXI Expansion In Pulse Width
— 6.5 — 10
3
— 6.5
tXIS
tSKEW1
Expansion In Set-Up Time
Skew time between Read Clock & Write Clock for FF/IR
and EF/OR
3 —5 —
5 —6 —
tSKEW2(4) Skew time between Read Clock & Write Clock for PAE
and PAF
14 — 18 —
Commercial
IDT72V205L20
IDT72V215L20
IDT72V225L20
IDT72V235L20
IDT72V245L20
Min. Max.
— 50
2 12
20 —
8—
8—
5—
1—
5—
1—
20 —
12 —
12 —
— 20
0—
3 10
3 10
— 12
— 12
— 22
— 12
— 22
— 12
— 22
— 12
8—
8—
8—
20 —
NOTES:
1. Industrial temperature range product for the 15ns speed grade is available as a standard device. All other speed grades are available by special order.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
4. tSKEW2 applies to synchronous PAE and synchronous PAF only.
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
OutputLoad
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1
5
3.3V
330
D.U.T.
510
30pF*
4294 drw 03
Figure 1. Output Load
* Includes jig and scope capacitances.

5 Page





IDT72V205L20PFI arduino
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
RS
REN, WEN, LD
FL, RXI, WXI (1)
tRS
tRSR
tRSS
tRSR
CONFIGURATION SETTING
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
RCLK, WCLK (2)
FF/IR
tRSF
(4)
IDT Standard Mode
FWFT Mode
EF/OR
tRSF
FWFT Mode
IDT Standard Mode
PAF, WXO/
HF, RXO
PAE
tRSF
tRSF
Q0 - Q17
tRSF
OE = 1(3)
NOTES:
OE = 0
1. Single device mode (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0). FL, RXI, WXI should be static (tied to VCC or GND).
2. The clocks (RCLK, WCLK) can be free-running asynchronously or coincidentally.
3. After reset, the outputs will be LOW if OE = 0 and tri-state if OE = 1.
4. In FWFT mode IR goes LOW based on the WCLK edge after Reset.
Figure 5. Reset Timing(2)
4294 drw 05
WCLK
D0 - D17
WEN
FF
RCLK
tCLKH
tCLK
tCLKL
tDS
DATA IN VALID
tENS
tWFF
tSKEW1 (1)
tDH
tENH
tWFF
NO OPERATION
REN
4294 drw 06
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.
2. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
Figure 6. Write Cycle Timing with Single Register-Buffered FF (IDT Standard Mode)
11

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