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PDF IDT72V19320 Data sheet ( Hoja de datos )

Número de pieza IDT72V19320
Descripción 3.3V MULTIMEDIA FIFO 16 BIT V-III/ 32 BIT Vx-III FAMILY UP TO 1 Mb DENSITY
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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No Preview Available ! IDT72V19320 Hoja de datos, Descripción, Manual

3.3V MULTIMEDIA FIFO
16 BIT V-III, 32 BIT Vx-III FAMILY
UP TO 1 Mb DENSITY
IDT72V15160
IDT72V16160
IDT72V17160
IDT72V18160
IDT72V19160
IDT72V14320
IDT72V15320
IDT72V16320
IDT72V17320
IDT72V18320
IDT72V19320
FEATURES:
Choose among the following memory organizations: Commercial
V-III
IDT72V15160 - 4,096 x 16
IDT72V16160 - 8,192 x 16
IDT72V17160 - 16,384 x 16
IDT72V18160 - 32,768 x 16
IDT72V19160 - 65,536 x 16
Vx-III
IDT72V14320 - 1,024 x 32
IDT72V15320 - 2,048 x 32
IDT72V16320 - 4,096 x 32
IDT72V17320 - 8,192 x 32
IDT72V18320 - 16,384 x 32
IDT72V19320 - 32,768 x 32
Up to 100 MHz Operation of the Clocks
5V input tolerant
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Empty, Full and Half-Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
Program programmable flags through serial input
Output enable puts data outputs into high impedance state
JTAG port, provided for Boundary Scan function (PBGA Only)
Available in a 80-pin (V-III) Thin Quad Flat Pack, 128-pin(Vx-III)
Thin Quad Flat Pack (TQFP) or a 144-pin (Vx-III) Plastic Ball Grid
Array (PBGA) (with additional features)
Industrial temperature range (–40°C to +85°C)
High-performance submicron CMOS technology
FUNCTIONAL BLOCK DIAGRAM
*Available on the Vx-III PBGA package only.
WCLK
WEN
D0 - Dn
Data In
x16, x32
TCK
*TRST
* TMS
* TDI
**TDO
WRITE
CONTROL
MRS PRS
RESET LOGIC
READ
CONTROL
FIFO ARRAY
JTAG CONTROL
(BOUNDARY
SCAN)
*
FLAG LOGIC
LD SI FSEL1 EF
HF FF
SEN PFM FSEL0
PAE PAF
RCLK
REN
OE
Q0 - Qn
Data Out
x16, x32
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IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
NOVEMBER 2003
DSC-6163/2

1 page




IDT72V19320 pdf
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
INDUSTRIAL
TEMPERATURE RANGE
PIN DESCRIPTION
Symbol
Name
I/O
Description
D0–Dn DataInputs
I Data inputs for a 16 or 32-bit bus
EF Empty Flag
O EF indicates the FIFO memory is empty. See Table 2.
FF Full Flag
O FF indicates the FIFO memory is full. See Table 2.
FSEL0(1) Flag Select Bit 0
I During Master Reset, this input along with FSEL1 and the LD pin, will select the default offset values for the
programmable flags PAE and PAF. There are up to eight possible settings available.
FSEL1(1) Flag Select Bit 1
I During Master Reset, this input along with FSEL0 and the LD pin will select the default offset values for the
programmable flags PAE and PAF. There are up to eight possible settings available.
HF Half-Full Flag O HF indicates the FIFO memory is more than half-full. HF is asserted when the number of words written into the FIFO
reaches N÷2+1, where N is the total depth of the FIFO. See Table 2.
LD Load
I During Master Reset, the state of the LD input along with FSEL0 and FSEL1, determines one of eight default offset
values for the PAE and PAF flags and serial programming mode. After Master Reset, LD must be high and should
only toggle LOW together withSEN to start serial loading of the flag offsets.
MRS MasterReset
I MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Master Reset,
the FIFO is configured for one of eight programmable flag default settings, serial programming of the offset settings and
synchronous versus asynchronous programmable flag timing modes.
OE OutputEnable I OE controls the output line drivers.
PAE Programmable O PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the Empty Offset
Almost-Empty Flag
register. PAE goes HIGH if the number of words in the FIFO memory is greater than or equal to offset n.
PAF Programmable O PAF goes HIGH if the number of free locations in the FIFO memory is more than offset m, which is stored in the
Almost-Full Flag
Full Offset register. PAF goes LOW if the number of free locations in the FIFO memory is less than or equal to m.
PFM(1)
PRS
Programmable
Flag Mode
Partial Reset
Q0–Qn
RCLK
REN
SEN
Data Outputs
Read Clock
Read Enable
Serial Enable
I During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on PFM
will select SynchronousProgrammable flag timing mode.
I PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Partial Reset,
the serial programming method or programmable flag settings are all retained.
O Data outputs for an 16 or 32-bit bus. Outputs are not 5V tolerant regardless of the state of OE.
I When enabled by REN, the rising edge of RCLK reads data from the FIFO memory.
I REN enables RCLK for reading data from the FIFO memory.
I SEN enables serial loading of programmable flag offsets. SEN must be high during Master Reset and should only
toggle LOW together with LD to start serial loading of the flag offsets.
SI
WCLK
WEN
Serial In
Write Clock
Write Enable
I At Maser Reset this pin is LOW. After Master Reset, this pin functions as a serial input for loading offset registers.
I Enabled by WEN, the rising edge of WCLK writes data into the FIFO.
I WEN enables WCLK for writing data into the FIFO memory.
VCC +3.3V Supply
I These are VCC supply inputs and must be connected to the 3.3V supply rail.
GND Ground
I Ground Pins.
NOTE:
1. Inputs should not change state after Master Reset.
**Please continue to next page for more Pin descriptions for PBGA package.
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IDT72V19320 arduino
IDT72V15160/16160/17160/18160/19160
- 3.3V 16-BIT V-III MULTIMEDIA FIFO
IDT72V14320/15320/16320/17320/18320/19320 - 3.3V 32-BIT VX-III MULTIMEDIA FIFO
INDUSTRIAL
TEMPERATURE RANGE
TABLE 2 STATUS FLAGS FOR IDT STANDARD MODE
IDT72V15160
Number of
Words in
FIFO
IDT72V14320
0
1 to n(1)
(n+1) to 512
513 to (1,024-(m+1))
(1,024-m) to 1,023
1,024
IDT72V15320
0
1 to n(1)
(n+1) to 1,024
1,025 to (2,048-(m+1))
(2,048-m) to 2,047
2,048
IDT72V16320
0
1 to n(1)
(n+1) to 2,048
2,049 to (4,096-(m+1))
(4,096m) to 4,095
4,096
FF PAF HF PAE EF
HHHL L
H HH L H
H HHH H
H HL H H
HLLH H
L LLH H
Number of
Words in
FIFO
IDT72V16160
IDT72V17320
0
1 to n(1)
(n+1) to 4,096
4,097 to (8,192-(m+1))
(8,192-m) to 8,191
8,192
NOTE:
1. See Table 1 for values for n, m.
IDT72V17160
IDT72V18160
IDT72V19160
IDT72V18320
0
1 to n(1)
(n+1) to 8,192
8,193 to (16,384-(m+1))
(16,384-m) to 16,383
16,384
IDT72V19320
0
1 to n(1)
(n+1) to 16,384
16,385 to (32,768-(m+1))
(32,768-m) to 32,767
32,768
FF PAF HF PAE EF
0
1 to n(1)
(n+1) to 32,768
32,769 to (65,536-(m+1))
(65,536-m) to 65,535
65,536
H
H
H
H
H
L
HHL
HH L
HHH
HL H
LLH
LLH
L
H
H
H
H
H
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