|
|
PDF IDT72V12165 Data sheet ( Hoja de datos )
| Número de pieza | IDT72V12165 | |
| Descripción | 3.3 VOLT MULTIMEDIA FIFO 256 x 16/ 512 x 16/ 1/024 x 16/ 2/048 x 16/ and 4/096 x 16 | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de IDT72V12165 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
|
No Preview Available !
3.3 VOLT MULTIMEDIA FIFO
256 x 16, 512 x 16,
1,024 x 16, 2,048 x 16,
and 4,096 x 16
IDT72V11165, IDT72V12165
IDT72V13165, IDT72V14165
IDT72V15165
FEATURES
• 256 x 16-bit organization array (IDT72V11165)
• 512 x 16-bit organization array (IDT72V12165)
• 1,024 x 16-bit organization array (IDT72V13165)
• 2,048 x 16-bit organization array (IDT72V14165)
• 4,096 x 16-bit organization array (IDT72V15165)
• 15 ns read/write cycle time
• 5V input tolerant
• Independent Read and Write Clocks
• Empty/Full and Half-Full flag capability
• Output enable puts output data bus in high-impedance state
• Available in a 64-lead thin quad flatpack (10x10mm and 14x14mm
TQFP)
• Industrial temperature range (–40°C to +85°C)
DESCRIPTION
The IDT72V11165/72V12165/72V13165/72V14165/72V15165 devices
are First-In, First-Out (FIFO) memories with clocked read and write controls.
TheseFIFOshave16-bitinputandoutputports. Theinputportiscontrolled
by a free-running clock (WCLK), and an input enable pin (WEN). Data is written
into the Multimedia FIFO on every clock when WEN is asserted. The output port
is controlled by another clock pin (RCLK) and another enable pin (REN). The
Read Clock (RCLK) can be tied to the Write Clock for single clock operation or
the two clocks can run asynchronous of one another for dual-clock operation.
An Output Enable pin (OE) is provided on the read port for three-state control
of the output.
These Multimedia FIFOs support three fixed flags: Empty Flag (EF), Full
Flag (FF), and Half Full Flag (HF).
FUNCTIONAL BLOCK DIAGRAM
WCLK
WEN
WRITE
CONTROL
D0 - D15
Data In
x16
FIFO ARRAY
RESET LOGIC
RS
READ
CONTROL
RCLK
REN
OE
Q0 - Q15
Data Out
x16
FLAG OUTPUTS
EF HF FF
6359 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
NOVEMBER 2003
DSC-6359/2
1 page  
IDT72V11165/72V12165/72V13165/72V14165/72V15165 3.3V MULTIMEDIA FIFO
256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16 and 4,096 x 16
INDUSTRIAL
TEMPERATURERANGE
FUNCTIONAL DESCRIPTION
WRITE/READ AND FLAG FUNCTION
To write data into to the FIFO, Write Enable (WEN) must be LOW. Data
presented to the DATA IN lines will be clocked into the FIFO on subsequent
transitions of the Write Clock (WCLK). After the first write is performed, the Empty
Flag (EF) will go HIGH. Subsequent writes will continue to fill up the FIFO.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the Half-Full Flag (HF) would toggle to LOW once
the 129th (72V11165), 257th (72V12165), 513th (72V13165), 1,025th
(72V14165), and 2,049th (72V15165) word respectively was written into the
FIFO.
When the FIFO is full, the Full Flag (FF)willgoLOW,inhibitingfurtherwrite
operations. Ifnoreadsareperformedafterareset,FFwillgoLOWafterDwrites
to the FIFO. D = 256 writes for the IDT72V11165, 512 for the IDT72V12165,
1,024 for the IDT72V13165, 2,048 for the IDT72V14165 and 4,096 for the
IDT72V15165, respectively.
If the FIFO is full, the first read operation will cause FF to go HIGH.
Subsequent read operations will cause the Half-Full Flag (HF) to go HIGH.
Continuing read operations will cause the FIFO to be empty. When the last word
has been read from the FIFO, the EF will go LOW inhibiting further read
operations. REN is ignored when the FIFO is empty.
SIGNAL DESCRIPTIONS
INPUTS
DATA IN (D0 - D15)
Data inputs for 16-bit wide data.
CONTROLS
RESET (RS)
Reset is accomplished whenever the Reset (RS) input is taken to a LOW
state. During reset, both internal read and write pointers are set to the first
location. A reset is required after power-up before a write operation can take
place. The Half-Full Flag (HF) to HIGH after tRSF. The Full Flag (FF) will reset
toHIGH. TheEmptyFlag(EF)willresettoLOW.Duringreset,theoutputregister
isinitializedtoallzerosandtheoffsetregistersareinitializedtotheirdefaultvalues.
WRITE CLOCK (WCLK)
A write cycle is initiated on the LOW-to-HIGH transition of the Write Clock
(WCLK).DatasetupandholdtimesmustbemetwithrespecttotheLOW-to-HIGH
transition of WCLK.
The Write and Read Clocks can be asynchronous or coincident.
WRITE ENABLE (WEN)
WhentheWEN input isLOW,datamaybeloadedintotheFIFORAMarray
on the rising edge of every WCLK cycle if the device is not full. Data is stored
in the RAM array sequentially and independently of any ongoing read
operation.
When WEN is HIGH, no new data is written in the RAM array on each WCLK
cycle.
To prevent data overflow, FF will go LOW, inhibiting further write operations.
Upon the completion of a valid read cycle, FF will go HIGH allowing a write to
occur. The FF flag is updated on the rising edge of WCLK.
READ CLOCK (RCLK)
Data can be read on the outputs on the LOW-to-HIGH transition of the Read
Clock (RCLK), when Output Enable (OE) is set LOW.
The Write and Read Clocks can be asynchronous or coincident.
READ ENABLE (REN)
WhenReadEnableisLOW,dataisloadedfromtheRAMarrayintotheoutput
register on the rising edge of every RCLK cycle if the device is not empty.
When the REN input is HIGH, the output register holds the previous data and
nonewdataisloadedintotheoutputregister. ThedataoutputsQ0-Qnmaintain
the previous data value.
Every word accessed at Qn, including the first word written to an empty FIFO,
mustberequestedusingREN. WhenthelastwordhasbeenreadfromtheFIFO,
the Empty Flag (EF) will go LOW, inhibiting further read operations. REN is
ignored when the FIFO is empty. Once a write is performed, EF will go HIGH
allowing a read to occur. The EF flag is updated on the rising edge of RCLK.
OUTPUT ENABLE (OE)
When Output Enable (OE) is enabled (LOW), the parallel output buffers
receive data from the output register. When OE is disabled (HIGH), the Q output
data bus is in a high-impedance state.
OUTPUTS
FULL FLAG/INPUT READY (FF)
When the FIFO is full, FF will go LOW, inhibiting further write operations.
When FF is HIGH, the FIFO is not full. If no reads are performed after a reset,
FFwillgoLOWafterDwritestotheFIFO. D=256writesfortheIDT72V11165,
512 for the IDT72V12165, 1,024 for the IDT72V13165, 2,048 for the
IDT72V14165 and 4,096 for the IDT72V15165.
FF is synchronous and updated on the rising edge of WCLK.
EMPTY FLAG/OUTPUT READY (EF)
WhentheFIFOisempty, EFwillgoLOW,inhibitingfurtherreadoperations.
When EF is HIGH, the FIFO is not empty.
EF is synchronous and updated on the rising edge of RCLK.
HALF-FULL FLAG (HF)
Afterhalfofthememoryisfilled,andattheLOW-to-HIGHtransitionofthenext
write cycle, the Half-Full Flag goes LOW and will remain set until the difference
between the write pointer and read pointer is less than or equal to one half of
the total memory of the device. The Half-Full Flag (HF) is then reset to HIGH
by the LOW-to-HIGH transition of the Read Clock (RCLK). The HF is
asynchronous.
DATA OUTPUTS (Q0-Q15)
Data outputs for 16-bit wide data.
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet IDT72V12165.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| IDT72V12165 | 3.3 VOLT MULTIMEDIA FIFO 256 x 16/ 512 x 16/ 1/024 x 16/ 2/048 x 16/ and 4/096 x 16 | Integrated Device Technology |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |