PDF IDT7284 Data sheet ( Hoja de datos )

Número de pieza	IDT7284
Descripción	CMOS DUAL ASYNCHRONOUS FIFO DUAL 256 x 9/ DUAL 512 x 9/DUAL 1/024 x 9/ DUAL 2/048 x 9/DUAL 4/096 x 9/ DUAL 8/192 x 9
Fabricantes	Integrated Device Technology
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No Preview Available ! CMOS DUAL ASYNCHRONOUS FIFO DUAL 256 x 9, DUAL 512 x 9, DUAL 1,024 x 9, DUAL 2,048 x 9, DUAL 4,096 x 9, DUAL 8,192 x 9 IDT7280 IDT7281 IDT7282 IDT7283 IDT7284 IDT7285 FEATURES: • The IDT7280 is equivalent to two IDT7200 256 x 9 FIFOs • The IDT7281 is equivalent to two IDT7201 512 x 9 FIFOs • The IDT7282 is equivalent to two IDT7202 1,024 x 9 FIFOs • The IDT7283 is equivalent to two IDT7203 2,048 x 9 FIFOs • The IDT7284 is equivalent to two IDT7204 4,096 x 9 FIFOs • The IDT7285 is equivalent to two IDT7205 8,192 x 9 FIFOs • Low power consumption — Active: 685 mW (max.) — Power-down: 83 mW (max.) • Ultra high speed—12 ns access time • Asynchronous and simultaneous read and write • Offers optimal combination of data capacity, small foot print and functional flexibility • Ideal for bi-directional, width expansion, depth expansion, bus-matching, and data sorting applications • Status Flags: Empty, Half-Full, Full • Auto-retransmit capability • High-performance CMOS technology • Space-saving TSSOP • Industrial temperature range (–40°C to +85°C) is available DESCRIPTION: The IDT7280/7281/7282/7283/7284/7285 are dual-FIFO memories that load and empty data on a first-in/first-out basis. These devices are functional and compatible to two IDT7200/7201/7202/7203/7204/7205 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. The devices use Full and Empty flags to prevent data overflow and underflow and expansion logic to allow for unlimited expansion capability in both word size and depth. The reads and writes are internally sequential through the use of ring pointers, with no address information required to load and unload data. Data is toggled in and out of the devices through the use of the Write (W) and Read (R) pins. The devices utilize a 9-bit wide data array to allow for control and parity bits at the user’s option. This feature is especially useful in data communications applications where it is necessary to use a parity bit for transmission/reception error checking. It also features a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW to allow for retransmission from the beginning of data. A Half-Full Flag is available in the single device mode and width expansion modes. These FIFOs are fabricated using IDT’s high-speed CMOS technology. They are designed for those applications requiring asynchronous and simul- taneous read/writes in multiprocessing and rate buffer applications. FUNCTIONAL BLOCK DIAGRAM DA(DTAA0IN-DPAU8T) S RSA WA WRITE CONTROL WRITE POINTER RAM ARRAY A 256 x 9 512 x 9 1,024 x 9 2,048 x 9 4,096 x 9 8,192 x 9 READ POINTER THREE- STATE BUFFERS RA READ CONTROL FLAG LOGIC EXPANSION LOGIC RESET LOGIC XIA XOA/HFA FFA EFA DATA FLA/RTA OUTPUTS (QA0-QA8) WB WRITE CONTROL DA(DTAB0IN-DPBU8T) S RSB WRITE POINTER THREE- STATE BUFFERS RAM ARRAY B 256 x 9 512 x 9 1,024 x 9 2,048 x 9 4,096 x 9 8,192 x 9 READ POINTER READ CONTROL FLAG LOGIC EXPANSION LOGIC RB XIB XOB/HFB FFB EFB DATA OUTPUTS (QB0-QB8) RESET LOGIC FLB/RTB 3208 drw 01 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 1 2002 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. SEPTEMBER 2002 DSC-3208/5 1 page IDT7280/7281/7282/7283/7284/7285 5V ASYNCHRONOUS FIFO DUAL 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 RS W R EF HF, FF tRSC tRS tRSS tRSS tEFL tHFH , tFFH NOTES: 1. EF, FF, HF may change status during Reset, but flags will be valid at tRSC. 2. W and R = VIH around the rising edge of RS. Figure 2. Reset COMMERCIALTEMPERATURERANGE tRSR 3208 drw 04 R Q0-Q8 W D0-D8 t RC tA tRR t RPW tA t RLZ t WPW t DV DATA OUT VALID t WC t WR t RHZ DATA OUT VALID t DS t DH DATA IN VALID DATA IN VALID Figure 3. Asynchronous Write and Read Operation 3208 drw 05 LAST WRITE IGNORED WRITE FIRST READ ADDITIONAL FIRST READS WRITE R W tWFF FF tRFF Figure 4. Full Flag From Last Write to First Read 5 3208 drw 06 5 Page IDT7280/7281/7282/7283/7284/7285 5V ASYNCHRONOUS FIFO DUAL 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 DATA IN W R COMMERCIALTEMPERATURERANGE tRPE EF DATA OUT tWLZ tWEF tA tREF DATA OUT VALID Figure 17. Read Data Flow-Through Mode 3208 drw 19 R W FF DATA IN DATA OUT tRFF tA DATA OUT VALID Figure 18. Write Data Flow-Through Mode tWPF tWFF DATA IN VALID tDS tDH 3208 drw 20 11 11 Page

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