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PDF IDT72801 Data sheet ( Hoja de datos )

Número de pieza IDT72801
Descripción DUAL CMOS SyncFIFO
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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DUAL CMOS SyncFIFO
Integrated Device Technology, Inc.
IDT72801
IDT72811
IDT72821
IDT72831
IDT72841
FEATURES:
• The 72801 is equivalent to two 72201 256 x 9 FIFOs
• The 72811 is equivalent to two 72211 512 x 9 FIFOs
• The 72821 is equivalent to two 72221 1024 x 9 FIFOs
• The 72831 is equivalent to two 72231 2048 x 9 FIFOs
• The 72841 is equivalent to two 72241 4096 x 9 FIFOs
• Offers optimal combination of large capacity, high speed,
design flexibility and small footprint
• Ideal for prioritization, bidirectional, and width expansion
applications
• 15 ns read/write cycle time FOR THE 72801/72811
• 20 ns read/write cycle time FOR THE 72821/72831/72841
• Separate control lines and data lines for each FIFO
• Separate empty, full, programmable almost-empty and
almost-full flags for each FIFO
• Enable puts output data lines in high-impedance state
• Space-saving 64-pin Thin Quad Flat Pack (TQFP)
• Industrial temperature range (-40OC to +85OC) is avail-
able, tested to military electrical specifications
DESCRIPTION:
72801/72811/72821/72831/72841 are dual synchronous
(clocked) FIFOs. The device is functionally equivalent to two
72201/72211/72221/72231/72241 FIFOs in a single package
with all associated control, data, and flag lines assigned to
separate pins.
Each of the two FIFOs (designated FIFO A and FIFO B)
contained in the 72801/72811/72821/72831/72841 has a 9-
bit input data port (DA0 - DA8), DB0 - DB8) and a 9-bit output
data port (QA0 - QA8, QB0 - QB8). Each input port is
controlled by a free-running clock(WCLKA, WCLKB), and two
write enable pins (WENA1, WENA2, WENB1, WENB2). Data
is written into each of the two arrays on every rising clock edge
of the write clock (WCLKA WCLKB) when the appropriate
write enable pins are asserted.
The output port of each FIFO bank is controlled by its
associated clock pin (RCLKA, RCLKB) and two read enable
pins (RENA1, RENA2, RENB1, RENB2). The read clock can
be tied to the write clock for single clock operation or the two
clocks can run asynchronous of one another for dual clock
operation. An output enable pin (OEA, OEB) is provided on the
read port of each FIFO for three-state output control .
Each of the two FIFOs has two fixed flags, empty (EFA, EFB)
and full (FFA, FFB). Two programmable flags, almost-empty
(PAEA, PAEB) and almost-full (PAFA, PAFB), are provided for
PIN CONFIGURATION
QA1
QA2
QA3
QA4
QA5
QA6
QA7
QA8
VCC
WENA2/LDA
WCLKA
WENA1
RSA
DA8
DA7
DA6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PN64-1
TQFP,
TOP VIEW
48 QB0
47 FFB
46 EFB
45 OEB
44 RENB2
43 RCLKB
42 RENB1
41 GND
40 VCC
39 PAEB
38 PAFB
37 DB0
36 DB1
35 DB2
34 DB3
33 DB4
3034 drw 01
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
5.15
NOVEMBER 1996
DSC-3034/1
1

1 page




IDT72801 pdf
72801/72811/72821/72831/72841 DUAL CMOS SyncFIFO
256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
COMMERCIAL TEMPERATURE
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C)
Commercial
IDT72801L12 IDT72801L15 IDT72801L20 IDT72801L25 IDT72801L35
IDT72811L12 IDT72811L15 IDT72811L20 IDT72811L25 IDT72811L35
IDT72821L12 IDT72821L15 IDT72821L20 IDT72821L25 IDT72821L35
IDT72831L12 IDT72831L15 IDT72831L20 IDT72831L25 IDT72831L35
IDT72841L12 IDT72841L15 IDT72841L20 IDT72841L25 IDT72841L35
Symbol Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
fS Clock Cycle Frequency
— 83.3 — 66.7 — 50
— 40
— 28.6 MHz
tA Data Access Time
28
2 10
2 12
3 15
3 20 ns
tCLK Clock Cycle Time
12 —
15 —
20 —
25 —
35 — ns
tCLKH Clock High Time
5—
6—
8—
10 —
14 — ns
tCLKL Clock Low Time
5—
6—
8—
10 —
14 — ns
tDS Data Set-up Time
3—
4—
5—
6—
8 — ns
tDH Data Hold Time
0—
1—
1—
1—
2 — ns
tENS Enable Set-up Time
3—
4—
5—
6—
8 — ns
tENH
tRS
Enable Hold Time
Reset Pulse Width(1)
0—
12 —
1—
15 —
1—
20 —
1—
25 —
2 — ns
35 — ns
tRSS Reset Set-up Time
12 —
15 —
20 —
25 —
35 — ns
tRSR Reset Recovery Time
12 —
15 —
20 —
25 —
35 — ns
tRSF Reset to Flag Time and Output Time
— 12
— 15
— 20
— 25
— 35 ns
tOLZ Output Enable to Output in Low-Z(2)
0—
0—
0—
0—
0 — ns
tOE Output Enable to Output Valid
37
38
3 10
3 13
3 15 ns
tOHZ Output Enable to Output in High-Z(2)
37
38
3 10
3 13
3 15 ns
tWFF Write Clock to Full Flag
—8
— 10
— 12
— 15
— 20 ns
tREF Read Clock to Empty Flag
—8
— 10
— 12
— 15
— 20 ns
tPAF Write Clock to Programmable
Almost-Full Flag
—8
— 10
— 12
— 15
— 20 ns
tPAE Read Clock to Programmable
Almost-Empty Flag
—8
— 10
— 12
— 15
— 20 ns
tSKEW1 Skew Time Between Read
Clock and Write Clock
for Empty Flag and Full Flag
5—
6—
8—
10 —
12 — ns
tSKEW2 Skew Time Between Read Clock
and Write Clock for Programmable
Almost-Empty Flag and
Programmable Almost-Full Flag
22 —
28 —
35 —
40 —
42 — ns
NOTES:
1. Pulse widths less than minimum values are not allowed.
2. Values guaranteed by design, not currently tested.
3034 tbl 07
5V
1.1K
AC TEST CONDITIONS
In Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1
3034 tbl 08
D.U.T.
680
30pF*
3034 drw 03
or equivalent circuit
Figure 1. Output Load
*Includes jig and scope capacitances.
5.15 5

5 Page





IDT72801 arduino
72801/72811/72821/72831/72841 DUAL CMOS SyncFIFO
256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
RCLKA (RCLKB)
tCLKH
tCLK
tCLKL
RENA1, RENA2
(RENB1, RENB2)
tENS
tENH
NO OPERATION
EFA (EFB)
QA0 - QA8
(QB0 - QB8)
OEA (OEB)
tREF
tA
tOLZ
tOE
VALID DATA
tOHZ
WCLKA, WCLKB
tSKEW1(1)
tREF
COMMERCIAL TEMPERATURE
WENA1 (WENB1)
WENA2 (WENB2)
3034 drw 08
NOTE:
1. tSKEW1 is the minimum time between a rising WCLKA (WCLKB) edge and a rising RCLKA (RCLKB) edge for EFA (EFB) to change during the current clock
cycle. If the time between the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW1, then EFA (EFB) may not change
state until the next RCLKA (RCLKB) edge.
Figure 6. Read Cycle Timing
5.15 11

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