PDF IDT72605 Data sheet ( Hoja de datos )

Número de pieza	IDT72605
Descripción	CMOS SyncBiFIFOO 256 x 18 x 2 and 512 x 18 x 2
Fabricantes	Integrated Device Technology
Logotipo
Hay una vista previa y un enlace de descarga de IDT72605 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas
No Preview Available ! CMOS SyncBiFIFO™ 256 x 18 x 2 and 512 x 18 x 2 IDT72605 IDT72615 Integrated Device Technology, Inc. FEATURES: • Two independent FIFO memories for fully bidirectional data transfers • 256 x 18 x 2 organization (IDT 72605) • 512 x 18 x 2 organization (IDT 72615) • Synchronous interface for fast (20ns) read and write cycle times • Each data port has an independent clock and read/write control • Output enable is provided on each port as a three-state control of the data bus • Built-in bypass path for direct data transfer between two ports • Two fixed flags, Empty and Full, for both the A-to-B and the B-to-A FIFO • Programmable flag offset can be set to any depth in the FIFO • The synchronous BiFIFO is packaged in a 64-pin TQFP (Thin Quad Flatpack), 68-pin PGA and 68-pin PLCC • Industrial temperature range (-40oC to +85oC) is avail- able, tested to military electrical specifications DESCRIPTION: The IDT72605 and IDT72615 are very high-speed, low- power bidirectional First-In, First-Out (FIFO) memories, with synchronous interface for fast read and write cycle times. The SyncBiFIFO™ is a data buffer that can store or retrieve information from two sources simultaneously. Two Dual-Port FIFO memory arrays are contained in the SyncBiFIFO; one data buffer for each direction. The SyncBiFIFO has registers on all inputs and outputs. Data is only transferred into the I/O registers on clock edges, hence the interfaces are synchronous. Each Port has its own independent clock. Data transfers to the I/O registers are gated by the enable signals. The transfer direction for each port is controlled independently by a read/write signal. Individ- ual output enable signals control whether the SyncBiFIFO is driving the data lines of a port or whether those data lines are in a high-impedance state. Bypass control allows data to be directly transferred from input to output register in either direction. The SyncBiFIFO has eight flags. The flag pins are full, empty, almost-full, and almost-empty for both FIFO memo- ries. The offset depths of the almost-full and almost-empty flags can be programmed to any location. The SyncBiFIFO is fabricated using IDT’s high-speed, submicron CMOS technology. FUNCTIONAL BLOCK DIAGRAM DA0-DA17 ENA R/WA OEA HIGH Z CONTROL CSA A2 A1 A0 EFAB PPAAEFAABB FFAB CLKA µP INTERFACE FLAG LOGIC CLKB INPUT REGISTER MEMORY ARRAY 512 x 18 256 x 18 MUX OUTPUT REGISTER OUTPUT REGISTER MUX MEMORY ARRAY 512 x 18 256 x 18 INPUT REGISTER RESET LOGIC FLAG LOGIC POWER SUPPLY RS EPPFFAAFBBFEAABBAA 3 VCC 7 GND OEB R/WB ENB HIGH Z CONTROL BYPB DB0-DB17 SyncBiFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGES ©1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391. 5.18 2704 drw 01 DECEMBER 1996 DSC-2704/5 1 1 page IDT72605/IDT72615 CMOS SyncBiFIFO 256 x 18 x 2 and 512 x 18 x 2 COMMERCIAL TEMPERATURE RANGE PIN DESCRIPTION (Continued) Symbol Name FFBA B→A Full Flag BYPB RS VCC GND Port B Bypass Flag Reset Power Ground I/O Description O When FFBA is LOW, the B→A FIFO is full and further data writes into Port B are inhibited. When FFBA is HIGH, the FIFO is not full. FFBA is synchronized to CLKB. In bypass mode, FFBA tells Port B that a message is waiting in Port A’s output register. If FFBA is LOW, a bypass message is in the register. If FFBA is HIGH, Port A has read the message and another message can be written into Port B. O This flag informs Port B that the Synchronous BiFIFO is in bypass mode. When BYPB is LOW, Port A has placed the FIFO into bypass mode. If BYPB is HIGH, the Synchronous BiFIFO passes data into memory. BYPB is synchronized to CLKB. I A LOW on this pin will perform a reset of all Synchronous BiFIFO functions. There are three +5V power pins for the PLCC and PGA packages and two for the TQFP. There are seven ground pins for the PLCC and PGA packages and four for the TQFP. ABSOLUTE MAXIMUM RATINGS(1) RECOMMENDED DC OPERATING CONDITIONS 2704 tbl 02 Symbol Rating Com’l. VTERM Terminal Voltage with Respect to Ground –0.5 to +7.0 TA Operating Temperature 0 to +70 TBIAS Temperature Under Bias –55 to +125 TSTG Storage Temperature –55 to +125 IOUT DC Output Current 50 Mil. Unit –0.5 to +7.0 V –55 to +125 °C –65 to +135 °C –65 to +150 °C 50 mA Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 4.5 5.0 5.5 V GND Supply Voltage 00 0V VIH Input High Voltage 2.0 — — V VIL(1) Input Low Voltage — — 0.8 V NOTE: 1. 1.5V undershoots are allowed for 10ns once per cycle. 2704 tbl 04 CAPACITANCE (TA = +25°C, F = 1.0MHz) NOTE: 2704 tbl 03 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT- INGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Symbol Parameter Conditions CIN(2) Input Capacitance VIN = 0V COUT(1,2) Output Capacitance VOUT = 0V NOTES: 1. With output deselected. 2. Characterized values, not currently tested. Max. Unit 10 pF 10 pF 2704 tbl 05 DC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C) Symbol Parameter IIL(1) IOL(2) VOH VOL ICC(3) Input Leakage Current (Any Input) Output Leakage Current Output Logic "1" Voltage IOUT = –2mA Output Logic "0" Voltage IOUT = 8mA Average VCC Power Supply Current NOTES: 1. Measurements with 0.4V ≤ VIN ≤ VCC. 2. OEA, OEB ≥ VIH; 0.4 ≤ VOUT ≤ VCC. 3. Tested with outputs open. Testing frequency f=20MHz Min. –1 –10 2.4 — — IDT72615L IDT72605L Commercial tCLK = 20, 25, 35, 50ns Typ. — — — — — Max. 1 10 — 0.4 230 Unit µA µA V V mA 2704 tbl 06 5.18 5 5 Page IDT72605/IDT72615 CMOS SyncBiFIFO 256 x 18 x 2 and 512 x 18 x 2 RS EF AB, PAE AB, EF BA, PAE BA EF AB, PAE AB, EF BA, PAE BA CSA, EN A, EN B tRS tRSF tRSF tRSS COMMERCIAL TEMPERATURE RANGE tRSR Figure 3. Reset Timing 2704 drw 07 CLKA A0 , A1 , A2 , R/WA CSA ENA FFAB DA0 -DA17 CLKB tCLKH tCLK tCLKL tFF tSKEW1 READ tCS tCH tFF tDS tDH DATA IN VALID NO READ OPERATION Figure 4. Port A (A→B) Write Timing NO OPERATION 2704 drw 08 5.18 11 11 Page

Páginas	Total 20 Páginas
PDF Descargar	[ Datasheet IDT72605.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
IDT72605	CMOS SyncBiFIFOO 256 x 18 x 2 and 512 x 18 x 2	Integrated Device Technology

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar