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PDF IDT72521 Data sheet ( Hoja de datos )

Número de pieza IDT72521
Descripción PARALLEL BIDIRECTIONAL FIFO 512 x 18 & 1024 x 18
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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Integrated Device Technology, Inc.
PARALLEL BIDIRECTIONAL FIFO
512 x 18 & 1024 x 18
IDT72511
IDT72521
FEATURES:
• Two side-by-side FIFO memory arrays for bidirectional
data transfers
• 512 x 18-Bit - 512 x 18-Bit (IDT72511)
• 1024 x 18-Bit - 1024 x 18-Bit (IDT72521)
• 18-bit data buses on Port A side and Port B side
• Can be configured for 18-to-18-bit or 36-to-36-bit com-
munication
• Fast 35ns access time
• Fully programmable standard microprocessor interface
• Built-in bypass path for direct data transfer between two
ports
• Two fixed flags, Empty and Full, for both the A-to-B and
the B-to-A FIFO
• Two programmable flags, Almost-Empty and Almost-Full
for each FIFO
• Programmable flag offset can be set to any depth in the
FIFO
• Any of the eight flags can be assigned to four external
flag pins
• Flexible reread/rewrite capabilities
• Six general-purpose programmable I/O pins
• Standard DMA control pins for data exchange with
peripherals
• 68-pin PGA and PLCC packages
DESCRIPTION:
The IDT72511 and IDT72521 are highly integrated first-in,
first-out memories that enhance processor-to-processor and
processor-to-peripheral communications. IDT BiFIFOs inte-
grate two side-by-side memory arrays for data transfers in
two directions.
The BiFIFOs have two ports, A and B, that both have
standard microprocessor interfaces. All BiFIFO operations
are controlled from the 18-bit wide Port A. Port B is also 18
bits wide and can be connected to another processor or a
peripheral controller. The BiFIFOs have a 9-bit bypass path
that allows the device connected to Port A to pass messages
directly to the Port B device.
Ten registers are accessible through Port A, a Com-
mand Register, a Status Register, and eight Configuration
Registers.
The IDT BiFIFO has programmable flags. Each FIFO
memory array has four internal flags, Empty, Almost-Empty,
Almost-Full and Full, for a total of eight internal flags. The
Almost-Empty and Almost-Full flag offsets can be set to any
depth through the Configuration Registers. These eight inter-
nal flags can be assigned to any of four external flag pins
(FLGA-FLGD) through one Configuration Register.
Port B has programmable I/O, reread/rewrite and DMA
functions. Six programmable I/O pins are manipulated through
SIMPLIFIED BLOCK DIAGRAM
18-Bit
FIFO
Data
18-bits
Port
A
Bypass
18-Bit
FIFO
9-bits
18-bits
Data
Port
B
Control
Flags
Processor
Interface
A
Registers
Programmable
I/O Logic
Processor
Interface
B
Programmable
Flag Logic
Handshake
Interface
The IDT logo is a registered trademark of Integrated Device Techology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
5.32
I/O
Control
DMA
2668 drw 01
DECEMBER 1995
DSC-2668/6
1

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IDT72521 pdf
IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION
IDT’s BiFIFO family is versatile for both multiprocessor
and peripheral applications. Data can be sent through both
FIFO memories concurrently, thus freeing both processors
from laborious direct memory access (DMA) protocols and
frequent interrupts.
Two full 18-bit wide FIFOs are integrated into the IDT
BiFIFO, making simultaneous data exchange possible. Each
FIFO is monitored by separate internal read and write point-
ers, so communication is not only bidirectional, it is also
totally independent in each direction. The processor con-
nected to Port A of the BiFIFO can send or receive mes-
sages directly to the Port B device using the BiFIFO’s 9-bit
bypass path.
The BiFIFO can be used in different bus configurations:
18 bits to 18 bits and 36 bits to 36 bits. One BiFIFO can be
used for the 18- to 18-bit configuration, and two BiFIFOs are
required for 36- to 36-bit configuration. This configuration
can be extended to wider bus widths (54- to 54-bits, 72- to
72-bits, …) by adding more BiFIFOs to the configuration.
The microprocessor or microcontroller connected to Port
A controls all operations of the BiFIFO. Thus, all Port A
interface pins are inputs driven by the controlling processor.
Port B can be programmed to interface either with a second
processor or a peripheral device. When Port B is programmed
in processor interface mode, the Port B interface pins are
inputs driven by the second processor. If a peripheral device
is connected to the BiFIFO, Port B is programmed to periph-
eral interface mode and the interface pins are outputs.
18- to 18-bit Configurations
A single BiFIFO can be configured to connect an 18-bit
processor to another 18-bit processor or an 18-bit peripheral.
The upper BiFIFO shown in each of the Figures 1 and 2 can
be used in 18- to 18-bit configurations for processor and
peripheral interface modes respectively.
36- to 36-bit Configurations
In a 36- to 36-bit configuration, two BiFIFOs operate in
parallel. Both BiFIFOs are programmed simultaneously, 18
data bits to each device. Figures 1 and 2 show multiple
BiFIFOs configured for processor and peripheral interface
modes respectively.
Processor Interface Mode
When a microprocessor or microcontroller is connected to
Port B, all BiFIFOs in the configuration must be programmed
to processor interface mode. In this mode, all Port B inter-
face controls are inputs. Both REQ and CLK pins should be
pulled LOW to ensure that the setup and hold time require-
ments for these pins are met during reset. Figure 1 shows
the BiFIFO in processor interface mode.
Processor
A
Address
Control
IDT
BiFIFO
Cntl A
Cntl B
ACK
REQ
CLK
Data A Data B
Processor
B
Control
Data
36
IDT
BiFIFO
Data
36
RAM
Cntl A
Cntl B
ACK
REQ
CLK
Data A Data B
18
18
RAM
2668 drw 05
Figure 1. 36-Bit Processor to 36-Bit Processor Configuration
NOTE:
1. 36- to 36-bit processor interface configuration. Upper BiFIFO only is used in 18- to 18-bit configuration. Note that Cntl A refers to CSA, A1, A0, R/WA,
and DSA; Cntl B refers to R/WB and DSB or RB and WB.
5.32 5

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IDT72521 arduino
IDT72511/IDT72521
BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY
CONFIGURATION REGISTER 5 FORMAT
Bit Function
0 Select Port B Interface
RB and WB or DSB and R/WB
1 Unused
0
1
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Pins are RB and WB (Intel-style interface)
Pins are DSB and R/WB (Motorola-style interface)
2 Full Flag Definition
0 Write pointer meets read pointer
1 Write pointer meets reread pointer
3 Empty Flag Definition
0 Read pointer meets write pointer
1 Read pointer meets rewrite pointer
4 REQ Pin Polarity
0 REQ pin active HIGH
1 REQ pin active LOW
5 ACK Pin Polarity
0 ACK pin active LOW
1 ACK pin active HIGH
7-6 REQ / ACK Timing
00 2 internal clocks between REQ assertion and ACK assertion
01 3 internal clocks between REQ assertion and ACK assertion
10 4 internal clocks between REQ assertion and ACK assertion
8 Port B Read & Write
Timing Control for Peripheral Mode
11 5 internal clocks between REQ assertion and ACK assertion
0 RB, WB, and DSB are asserted for 1 internal clock
1 RB, WB, and DSB are asserted for 2 internal clocks
9 Internal Clock
Frequency Control
0 Internal clock = CLK
1 Internal clock = CLK divided by 2
10 Port B Interface
Mode Control
0 Processor interface mode (Port B controls are inputs)
1 Peripheral interface mode (Port B controls are outputs)
11 Unused
12 Unused
13 Unused
14 Unused
15 Unused
Table 10. BiFIFO Configuration Register 5 Format
2668 tbl 12
CONFIGURATION REGISTER 6 FORMAT
15 6 5 4 3 2
Unused
PIO5
PIO4
PIO3
PIO2
Figure 4. BiFIFO Configuration Register 6 Format for Programmable I/O Data
1
PIO1
0
PIO0
2668 tbl 13
CONFIGURATION REGISTER 7 FORMAT
15
Unused
65
MIO5
4
MIO4
3
MIO3
2
MIO2
1
MIO1
Figure 5. BiFIFO Configuration Register 7 Format for Programmable I/O Direction Mask
0
MIO0
2668 tbl 14
5.32 11

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