|
|
PDF IDT72413 Data sheet ( Hoja de datos )
| Número de pieza | IDT72413 | |
| Descripción | CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de IDT72413 (archivo pdf) en la parte inferior de esta página. Total 11 Páginas | ||
|
No Preview Available !
Integrated Device Technology, Inc.
CMOS PARALLEL
64 x 5-BIT FIFO
WITH FLAGS
IDT72413
FEATURES:
• First-ln/First-Out Dual-Port memory—45MHz
• 64 x 5 organization
• Low-power consumption
— Active: 200mW (typical)
• RAM-based internal structure allows for fast fall-through
time
• Asynchronous and simultaneous read and write
• Expandable by bit width
• Cascadable by word depth
• Half-Full and Almost-Full/Empty status flags
• IDT72413 is pin and functionally compatible with the
MMI67413
• High-speed data communications applications
• Bidirectional and rate buffer applications
• High-performance CMOS technology
• Available in plastic DIP, CERDIP and SOIC
• Military product compliant to MIL-STD-883, Class B
• Industrial temperature range (-40oC to +85oC) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT72413 is a 64 x 5, high-speed First-In/First-Out
(FIFO) that loads and empties data on a first-in-first-out basis.
It is expandable in bit width. All speed versions are cascad-
able in depth.
The FIFO has a Half-Full Flag, which signals when it has 32
or more words in memory. The Almost-Full/Empty Flag is
active when there are 56 or more words in memory or when
there are 8 or less words in memory.
The IDT72413 is pin and functionally compatible to the
MMI67413. It operates at a shift rate of 45MHz. This makes it
ideal for use in high-speed data buffering applications. The
IDT72413 can be used as a rate buffer, between two digital
systems of varying data rates, in high-speed tape drivers, hard
disk controllers, data communications controllers and
graphics controllers.
The IDT72413 is fabricated using IDTs high-performance
CMOS process. This process maintains the speed and high
output drive capability of TTL circuits in low-power CMOS.
Military grade product is manufactured in compliance with
the latest revision of MIL-STD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
OUPUT ENABLE
(OE)
DATAIN
(D0-4 )
FIFO
INPUT
STAGE
(MR)
MASTER
RESET
INPUT (IR)
READY
SHIFT
IN (SI)
INPUT
CONTROL
LOGIC
64 x 5
MEMORY
ARRAY
REGISTER
CONTROL
LOGIC
FLAG
CONTROL
LOGIC
FIFO
OUTPUT
STAGE
DATA OUT
(Q0-4 )
OUTPUT
CONTROL
LOGIC
(SO)
(OR)
SHIFT
OUT
OUPUT
READY
HALF-FULL (HF)
ALMOST-FULL/
EMPTY (AF/E)
2748 drw 01
The IDT logo is a registered trademark of Integrated Device Technology,Inc.
FAST is a trademark of National Semiconductor, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
5.02
DECEMBER 1996
DSC-2748/7
1
1 page  
IDT72413
CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1
2748 tbl 07
STANDARD TEST LOAD
5V
OUTPUT
R1
TEST POINT
R2 30pF*
DESIGN TEST LOAD
5V
2KΩ
30pF*
or equivalent circuit
*Including scope and jig
2748 drw 03
RESISTOR VALUES FOR
STANDARD TEST LOAD
IOL R1
24mA
200Ω
12mA
390Ω
8mA
600Ω
Figure 1. Output Load
R2
300Ω
760Ω
1200Ω
2748 tbl 08
FUNCTIONAL DESCRIPTION:
DATA OUTPUT
The IDT72413, 65 x 5 FIFO is designed using a dual-port
RAM architecture as opposed to the traditional shift register
approach. This FIFO architecture has a write pointer, a read
pointer and control logic, which allow simultaneous read and
write operations. The write pointer is incremented by the
falling edge of the Shift In (Sl) control; the read pointer is
incremented by the falling edge of the Shift Out (SO). The
Input Ready (IR) signals when the FIFO has an available
memory location; Output Ready (OR) signals when there is
valid data on the output. Output Enable (OE) provides the
capability of three-stating the FIFO outputs.
Data is shifted out on the HIGH-to-LOW transition of Shift
Out (SO). This causes the internal read pointer to be ad-
vanced to the next word location. If data is present, valid data
will appear on the outputs and Output Ready (OR) will go
HIGH. If data is not present, Output Ready will stay LOW
indicating the FIFO is empty. The last valid word read from the
FIFO will remain at the FlFOs output when it is empty. When
the FIFO is not empty Output Ready (OR) goes LOW on the
LOW-to-HlGH transition of Shift Out.
FALL-THROUGH MODE
FIFO RESET
The FIFO must be reset upon power up using the Master
Reset (MR) signal. This causes the FIFO to enter an empty
state signified by Output Ready (OR) being LOW and Input
Ready (IR) being HIGH. In this state, the data outputs (Q0-4)
will be LOW.
DATA INPUT
Data is shifted in on the LOW-to-HIGH transition of Shift In
(Sl). This loads input data into the first word location of the
FIFO and causes the lnput Ready to go LOW. On the HlGH-
to-LOW transition of Shift In, the write pointer is moved to the
next word position and Input Ready (lR) goes HlGH indicating
the readiness to accept new data. If the FIFO is full, Input
Ready will remain LOW until a word of data is shifted out.
The FIFO operates in a Fall-Through Mode when data gets
shifted into an empty FIFO. After the fall-through delay the
data propagates to the output. When the data reaches the
output, the Output Ready (OR) goes HIGH.
A Fall-Through Mode also occurs when the FIFO is
completely full. When data is shifted out of the full FIFO a
location is available for new data. After a fall-through delay,
the lnput Ready goes HlGH. If Shift In is HIGH, the new data
can be written to the FIFO. The fall-through delay of a RAM-
based FIFO (one clock cycle) is far less than the delay of a
Shift register-based FIFO.
5.02 5
5 Page 
IDT72413
CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SHIFT IN
INPUT READY
DATA IN
SI OR
IR SO
D 0 Q0
D1 Q1
D2 Q2
D3 Q3
D 4 MR Q 4
SI OR
IR SO
D0 Q0
D1 Q1
D2 Q2
D3 Q3
D 4 MR Q 4
OUTPUT READY
SHIFT OUT
DATA OUT
MR 2748 drw 17
NOTE:
1. FIFOs can be easily cascaded to any desired depth. The handshaking and associated timing between the FIFOs are handled by the inherent timing
of the devices.
Figure 15. 128 x 5 Depth Expansion
ORDERING INFORMATION
IDT XXXXX X X
X
X
Device Type Power Speed Package Process/
Temperature
Range
Blank Commercial (0°C to+70°C)
B Military (–55°C to+125°C)Compliant to MIL-STD-883, Class B
P Plastic DIP (300 mils wide)
D Cerdip (300 mils wide)
SO Small Outline IC
45 Com’l. Only
35 Com'l. and Mil
25 Com’l. and Mil
Shift Frequency (fs)Speed in MHz
L Low Power
72413 64 x 5 FIFO
2748 drw 18
5.02 11
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet IDT72413.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| IDT72413 | CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS | Integrated Device Technology |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |