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PDF IDT723642L15PF Data sheet ( Hoja de datos )

Número de pieza IDT723642L15PF
Descripción CMOS SyncBiFIFOO 256 x 36 x 2/ 512 x 36 x 2/ 1024 x 36 x 2
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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Integrated Device Technology, Inc.
CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2,
1024 x 36 x 2
IDT723622
IDT723632
IDT723642
FEATURES:
• Free-running CLKA and CLKB may be asynchronous or
coincident (simultaneous reading and writing of data on a
single clock edge is permitted)
• Two independent clocked FIFOs buffering data in oppo-
site directions
• Memory storage capacity:
IDT723622–256 x 36 x 2
IDT723632–512 x 36 x 2
IDT723642–1024 x 36 x 2
• Mailbox bypass register for each FIFO
• Programmable Almost-Full and Almost-Empty flags
• Microprocessor Interface Control Logic
• IRA, ORA, AEA, and AFA flags synchronized by CLKA
• IRB, ORB, AEB, and AFB flags synchronized by CLKB
• Supports clock frequencies up to 67MHz
• Fast access times of 11ns
• Available in 132-pin Plastic Quad Flatpack (PQF) or
space-saving 120-pin Thin Quad Flatpack (PF)
• Low-power 0.8-Micron Advanced CMOS technology
• Industrial temperature range (-40oC to +85oC) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT723622/723632/723642 is a monolithic, high-speed,
low-power, CMOS Bidirectional SyncFIFO (clocked) memory
which supports clock frequencies up to 67MHz and have read
access times as fast as 11ns. Two independent 256/512/
1024x36 dual-port SRAM FIFOs on board each chip buffer
data in opposite directions. Each FIFO has flags to indicate
empty and full conditions and two programable flags (almost
FUNCTIONAL BLOCK DIAGRAM
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
RST1
FIFO1,
Mail1
Reset
Logic
36
Mail 1
Register
256 x 36
512 x 36
1024 x 36
SRAM
Write
Pointer
Read
Pointer
MBF1
36
IRA Status Flag
AFA Logic
FIFO 1
ORB
AEB
FS0
FS1
A0 - A35
ORA
AEA
Programmable Flag
Offset Registers
9
FIFO 2
Status Flag
Logic
B0 - B35
IRB
AFB
36
MBF2
Read
Pointer
Write
Pointer
256 x 36
512 x 36
1024 x 36
SRAM
Mail 2
Register
36
FIFO2,
Mail2
Reset
Logic
Port-B
Control
Logic
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
5.22
RST2
CLKB
CSB
W/RB
ENB
MBB
3022 drw 01
DECEMBER 1996
DSC-3022/3

1 page




IDT723642L15PF pdf
IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTIONS (CONT.)
Symbol
MBB
MBF1
MBF2
ORA
ORB
RST1
RST2
W/RA
W/RB
Name
Port-B Mailbox
Select
Mail1 Register
Flag
Mail2 Register
Flag
Output-Ready
Flag
Output-Ready
Flag
FIFO1 Reset
FIFO2 Reset
Port-A Write/
Read Select
Port-B Write/
Read Select
I/O
I
O
O
O
(Port A)
O
(Port B)
I
I
I
I
Description
A HIGH level on MBB chooses a mailbox register for a port-B read or
write operation. When the B0-B35 outputs are active, a HIGH level on
MBB selects data from the mail1 register or output and a LOW level selects
FIFO1 output-register data for output.
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data
to the mail1 register. Writes to the mail1 register are inhibited while MBF1 is
LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a port-B
read is selected and MBB is HIGH. MBF1 is set HIGH when FIFO1 is reset.
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the
mail2 register. Writes to the mail2 register are inhibited while MBF2 is LOW.
MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a port-A read is
selected and MBA is HIGH. MBF2 is also set HIGH when FIFO2 is reset.
ORA is synchronized to the LOW-to-HIGH transition of CLKA. When ORA is
LOW, FIFO2 is empty and reads from its memory are disabled. Ready data
is present on the output register of FIFO2 when ORA is HIGH. ORA is
forced LOW when FlFO2 is reset and goes HIGH on the third LOW-to-HIGH
transition of CLKA after a word is loaded to empty memory.
ORB is synchronized to the LOW-to-HIGH transition of CLKB. When ORB
is LOW, FlFO1 is empty and reads from its memory are disabled. Ready data
is present on the output register of FIFO1 when ORB is HIGH. ORB is forced LOW
when FIFO1 is reset and goes HIGH on the third LOW-to-HIGH transition of CLKB
after a word is loaded to empty memory.
To reset FIFO1, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH
transitions of CLKB must occur while RST1 is LOW. The LOW-to-HIGH transition
of RST1 latches the status of FSO and FS1 for AFA and AEB offset selection.
FIFO1 must be reset upon power up before data is written to its RAM.
To reset FIFO2, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH
transitions of CLKB must occur while RST2 is LOW. The LOW-to-HIGH transition
of RST2 latches the status of FSO and FS1 for AFB and AEA offset selection.
FIFO2 must be reset upon power up before data is written to its RAM.
A HIGH selects a write operation and a LOW selects a read operation on port A
for a LOW-to-HIGH transition of CLKA. The AO-A35 outputs are in
the HIGH impedance state when W/RA is HIGH.
A LOW selects a write operation and a HIGH selects a read operation on port B
for a LOW-to-HIGH transition of CLKB. The BO-B35 outputs are in the HIGH
impedance state when W/RB is LOW.
5.22 5

5 Page





IDT723642L15PF arduino
IDT723622/723632/723642 CMOS SyncBiFIFO
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
port-B operation.
The port-B control signals are identical to those of port A
with the exception that the port-B write/read select (W/RB) is
the inverse of the port-A write/read select (W/RA). The state
of the port-B data (B0-B35) outputs is controlled by the port-
B chip select (CSB) and port-B write/read select (W/RB). The
B0-B35 outputs are in the high-impedance state when either
CSB is HIGH or W/RB is LOW. The B0-B35 outputs are active
when CSB is LOW and W/RB is HIGH.
Data is loaded into FIFO2 from the B0-B35 inputs on a
LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is
LOW, ENB is HIGH, MBB is LOW, and IRB is HIGH. Data is
read from FIFO1 to the B0-B35 outputs by a LOW-to-HIGH
transition of CLKB when CSB is LOW, W/RB is HIGH, ENB is
HIGH, MBB is LOW, and ORB is HIGH (see Table 3) . FIFO
reads and writes on port B are independent of any concurrent
port-A operation.
The setup and hold time constraints to the port clocks for
the port chip selects and write/read selects are only for
enabling write and read operations and are not related to high-
impedance control of the data outputs. If a port enable is LOW
during a clock cycle, the port’s chip select and write/read
select may change states during the setup and hold time
window of the cycle.
When a FIFO output-ready flag is LOW, the next data
word is sent to the FIFO output register automatically by the
LOW-to-HIGH transition of the port clock that sets the output-
ready flag HIGH. When the output-ready flag is HIGH, an
available data word is clocked to the FIFO output register only
when a FIFO read is selected by the port’s chip select, write/
read select, enable, and mailbox select.
SYNCHRONIZED FIFO FLAGS
Each FIFO is synchronized to its port clock through at
least two flip-flop stages. This is done to improve flag-signal
reliability by reducing the probability of metastable events
when CLKA and CLKB operate asynchronously to one an-
other. ORA, AEA, IRA, and AFA are synchronized to CLKA.
ORB, AEB, IRB, and AFB are synchronized to CLKB. Tables
4 and 5 show the relationship of each port flag to FIFO1 and
FIF02.
CSA
H
L
L
L
L
L
L
L
W/RA
X
H
H
H
L
L
L
L
ENA
X
L
H
H
L
H
L
H
MBA
X
X
L
H
L
L
H
H
CLKA
X
X
X
X
A0-A35 OUTPUTS
In high-impedance state
In high-impedance state
In high-impedance state
In high-impedance state
Active, FIFO2 output register
Active, FIFO2 output register
Active, mail2 register
Active, mail2 register
Table 2. Port-A Enable Functlon Table
PORT FUNCTION
None
None
FIFO1 write
Mail1 write
None
FIFO2 read
None
Mail2 read (set MBF2 HIGH)
CSB
H
L
L
L
L
L
L
L
W/RB
X
L
L
L
H
H
H
H
ENB
X
L
H
H
L
H
L
H
MBB
X
X
L
H
L
L
H
H
CLKB
X
X
X
X
B0-B35 OUTPUTS
In high-impedance state
In high-impedance state
In high-impedance state
In high-impedance state
Active, FIFO1 output register
Active, FIFO1 output register
Active, mail1 register
Active, mail1 register
Table 3. Port-B Enable Function Table
PORT FUNCTION
None
None
FIFO2 write
Mail2 write
None
FIFO1 read
None
Mail1 read (set MBF1 HIGH)
5.22 11

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