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Número de pieza IDT723631L15PQF
Descripción CMOS SyncFIFOO 512 x 36/ 1024 x 36/ 2048 x 36
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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Integrated Device Technology, Inc.
CMOS SyncFIFO
512 x 36, 1024 x 36,
2048 x 36
IDT723631
IDT723641
IDT723651
FEATURES:
• Free-running CLKA and CLKB can be asynchronous or
coincident (permits simultaneous reading and writing of
data on a single clock edge)
• Clocked FIFO buffering data from Port A to Port B
• Storage capacity: IDT723631 - 512 x 36
IDT723641 - 1024 x 36
IDT723651 - 2048 x 36
• Synchronous read retransmit capability
• Mailbox register in each direction
• Programmable Almost-Full and Almost-Empty flags
• Microprocessor interface control logic
• Input-Ready (IR) and Almost-Full (AF) flags synchronized
by CLKA
• Output-Ready (OR) and Almost-Empty (AE) flags syn-
chronized by CLKB
• Low-power 0.8-micron advanced CMOS technology
• Supports clock frequencies up to 67 MHz
• Fast access times of 11 ns
• Available in 132-pin plastic quad flat package (PQF) or
space-saving 120-pin thin quad flat package (TQFP)
• Industrial temperature range (-40°C to +85°C) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT723631/723641/723651 is a monolithic high-
speed, low-power, CMOS clocked FIFO memory. It supports
clock frequencies up to 67 MHz and has read access times as
fast as 12ns. The 512/1024/2048 x 36 dual-port SRAM FIFO
buffers data from port A to Port B. The FIFO memory has
retransmit capability, which allows previously read data to be
accessed again. The FIFO has flags to indicate empty and full
conditions and two programmable flags (almost full and al-
most empty) to indicate when a selected number of words is
FUNCTIONAL BLOCK DIAGRAM
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
RST
Reset
Logic
A0 - A35
AIRF
36
Mail 1
Register
512 x 36
1024 x 36
2048 x 36
SRAM
Write Read
Pointer Pointer
Status Flag
Logic
MBF1
RTM
RFM
B0 - B35
OR
AE
FS0/SD
FS1/SEN
Flag Offset
10 Registers
Mail 2
Register
Port-B
Control
Logic
CLKB
CSB
W/RB
ENB
MBB
MBF2
3023 drw 01
The IDT logo is a registered trademark and SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1997 Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
MAY 1997
DSC-3023/3
1

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IDT723631L15PQF pdf
IDT723631/723641/723651 CMOS SyncFIFO
512 x 36, 1024 x 36, 2048 x 36
PIN DESCRIPTION (CONTINUED)
COMMERCIAL TEMPERATURE RANGE
Symbol
Name
MBF2 Mail2 Register Flag
OR Output-Ready Flag
RFM Read From Mark
RST Reset
RTM Retransmit Mode
W/RA Port-A Write/Read
Select
W/RB Port-B Write/Read
Select
I/O Description
O MBF2 is set LOW by the LOW-to-HIGH transition of CLKB that writes data to
the mail2 register. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA
when a port-A read is selected and MBA is HIGH. MBF2 is set HIGH by a
reset.
O OR is synchronized to the LOW-to-HIGH transition of CLKB. When OR is
LOW, the FIFO is empty and reads are disabled. Ready data is present in the
output register of the FIFO when OR is HIGH. OR is forced LOW during the
reset and goes HIGH on the third LOW-to-HIGH transition of CLKB after a
word is loaded to empty memory.
I When the FIFO is in retransmit mode, a HIGH on RFM enables a LOW-to-
HIGH transition of CLKB to reset the read pointer to the beginning retransmit
location and output the first selected retransmit data.
I To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-
HIGH transitions of CLKB must occur while RST is LOW. The LOW-to-HIGH
transition of RST latches the status of FS0 and FS1 for AF and AE offset
selection.
I When RTM is HIGH and valid data is present in the FIFO output register (OR
is HIGH), a LOW-to-HIGH transition of CLKB selects the data for the begin-
ning of a retransmit and puts the FIFO in retransmit mode. The selected word
remains the initial retransmit point until a LOW-to-HIGH transition of CLKB
occurs while RTM is LOW, taking the FIFO out of retransmit mode.
I A HIGH selects a write operation and a LOW selects a read operation on
port A for a LOW-to-HIGH transition of CLKA. The A0-A35 outputs are in the
high-impedance state when W/RA is HIGH.
I A LOW selects a write operation and a HIGH selects a read operation on
port B for a LOW-to-HIGH transition of CLKB. The B0-B35 outputs are in the
high-impedance state when W/RB is LOW.
3023 tbl 02
5

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IDT723631L15PQF arduino
IDT723631/723641/723651 CMOS SyncFIFO
512 x 36, 1024 x 36, 2048 x 36
COMMERCIAL TEMPERATURE RANGE
ready flag is HIGH, a memory location is free in the SRAM to
write new data. No memory locations are free when the input-
ready flag is LOW and attempted writes to the FIFO are
ignored.
Each time a word is written to a FIFO, its write pointer is
incremented. The state machine that controls an input-ready
flag monitors a write-pointer and read pointer comparator that
indicates when the FIFO SRAM status is full, full-1, or full-2.
From the time a word is read from a FIFO, its previous memory
location is ready to be written in a minimum of three cycles of
CLKA. Therefore, an input-ready flag is LOW if less than two
cycles of CLKA have elapsed since the next memory write
location has been read. The second LOW-to-HIGH transition
on CLKA after the read sets the input-ready flag HIGH, and
data can be written in the following cycle.
A LOW-to-HIGH transition on CLKA begins the first syn-
chronization cycle of a read if the clock transition occurs at
time tSKEW1 or greater after the read. Otherwise, the subse-
quent CLKA cycle may be the first synchronization cycle (see
Figure 7).
ALMOST-EMPTY FLAG (AE)
The almost-empty flag of a FIFO is synchronized to the
port clock that reads data from its array (CLKB). The state
machine that controls an almost-empty flag monitors a write-
pointer and read-pointer comparator that indicates when the
FIFO SRAM status is almost empty, almost empty+1, or
almost empty+2. The almost-empty state is defined by the
contents of register X. This register is loaded with a preset
value during a FIFO reset,programmed from port A, or pro-
grammed serially (see almost-empty flag and almost-full flag
offset programming above). The almost-empty flag is LOW
when the FIFO contains X or less words and is HIGH when the
FIFO contains (X+1) or more words. A data word present in
the FIFO output register has been read from memory.
Two LOW-to-HIGH transitions of CLKB are required after
a FIFO write for the almost-empty flag to reflect the new level
of fill; therefore, the almost-empty flag of a FIFO containing
(X+1) or more words remains LOW if two cycles of CLKB have
not elapsed since the write that filled the memory to the (X+1)
level. An almost-empty flag is set HIGH by the second LOW-
to-HIGH transition of CLKB after the FIFO write that fills
memory to the (X+1) level. A LOW-to-HIGH transition of
CLKB begins the first synchronization cycle if it occurs at time
tSKEW2 or greater after the write that fills the FIFO to (X+1)
words. Otherwise, the subsequent CLKB cycle may be the
first synchronization cycle (see Figure 8).
ALMOST-FULL FLAG (AF)
The almost-full flag of a FIFO is synchronized to the port
clock that writes data to its array (CLKA). The state machine
that controls an almost-full flag monitors a write-pointer and
read-pointer comparator that indicates when the FIFO SRAM
status is almost full, almost full-1, or almost full-2. The almost-
full state is defined by the contents of register Y. This register
is loaded with a preset value during a FIFO reset, programmed
from port A, or programmed serially (see almost-empty flag
and almost-full flag offset programming). The almost-full flag
is LOW when the number of words in the FIFO is greater than
or equal to (512-Y), (1024-Y), OR (2048-Y) for the IDT723631,
IDT723641, or IDT723651, respectively. The almost-full flag
is HIGH when the number of words in the FIFO is less than or
equal to [512-(Y+1)], [1024-(Y+1)], or [2048-(Y+1)] for the
IDT723631, IDT723641, or IDT723651, respectively. A data
word present in the FIFO output register has been read from
memory.
Two LOW-to-HIGH transitions of CLKA are required after
a FIFO read for its almost-full flag to reflect the new level of fill.
Therefore, the almost-full flag of a FIFO containing [512/1024/
2048-(Y+1)] or less words remains LOW if two cycles of CLKA
have not elapsed since the read that reduced the number of
words in memory to [512/1024/2048-(Y+1)]. An almost-full
flag is set HIGH by the second LOW-to-HIGH transition of
CLKA after the FIFO read that reduces the number of words
in memory to [512/1024/2048-(Y+1)]. A LOW-to-HIGH tran-
sition of CLKA begins the first synchronization cycle if it occurs
at time tSKEW2 or greater after the read that reduces the
number of words in memory to [512/1024/2048-(Y+1)]. Oth-
erwise, the subsequent CLKA cycle may be the first synchro-
nization cycle (see Figure 9).
Number of Words in the FIFO(1,2)
IDT723631
0
1 to X
(X+1) to [512-(Y+1)]
(512-Y) to 511
512
IDT723641
0
1 to X
(X+1) to [1024-(Y+1)]
(1024-Y) to 1023
1024
IDT723651
0
1 to X
(X+1) to [2048-(Y+1)]
(2048-Y) to 2047
2048
NOTES:
1. X is the almost-empty offset for AE. Y is the almost-full offset for AF.
2. When a word is present in the FIFO output register, its previous memory location is free.
Table 4. FIFO Flag Operation
Synchronized
to CLKB
OR AE
LL
HL
HH
HH
HH
Synchronized
to CLKA
AF IR
HH
HH
HH
LH
LL
3023 tbl 11
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