DataSheet.es    


PDF IDT723613L20PF Data sheet ( Hoja de datos )

Número de pieza IDT723613L20PF
Descripción CMOS Clocked FIFO With Bus Matching and Byte Swapping 64 x 36
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



Hay una vista previa y un enlace de descarga de IDT723613L20PF (archivo pdf) en la parte inferior de esta página.


Total 29 Páginas

No Preview Available ! IDT723613L20PF Hoja de datos, Descripción, Manual

Integrated Device Technology, Inc.
CMOS Clocked FIFO
With Bus Matching and Byte Swapping
64 x 36
IDT723613
FEATURES:
• Free-running CLKA and CLKB may be asynchronous or
coincident (permits simultaneous reading and writing of
data on a single clock edge)
• 64 x 36 storage capacity FIFO buffering data from Port A
to Port B
• Mailbox bypass registers in each direction
• Dynamic Port B bus sizing of 36-bits (long word), 18-bits
(word), and 9-bits (byte)
• Selection of Big- or Little-Endian format for word and byte
bus sizes
• Three modes of byte-order swapping on Port B
• Programmable Almost-Full and Almost-Empty flags
• Microprocessor interface control logic
FF, AF flags synchronized by CLKA
EF, AE flags synchronized by CLKB
• Passive parity checking on each Port
• Parity Generation can be selected for each Port
• Low-power advanced BiCMOS technology
• Supports clock frequencies up to 67 MHz
• Fast access times of 10 ns
• Available in 132-pin quad flatpack (PQF) or space-saving
120-pin thin quad flatpack (TQFP)
• Industrial temperature range (-40oC to +85oC) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT723613 is a monolithic, high-speed, low-power,
BiCMOS synchronous (clocked) FIFO memory which sup-
ports clock frequencies up to 67 MHz and has read-access
times as fast as 10 ns. The 64 x 36 dual-port SRAM FIFO
buffers data from port A to port B. The FIFO has flags to
indicate empty and full conditions, and two programmable
flags, Almost-Full (AF) and Almost-Empty (AE), to indicate
FUNCTIONAL BLOCK DIAGRAM
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
RST
ODD/
EVEN
Device
Control
36
Mail 1
Register
64 x 36
SRAM
Parity
Gen/Check
MBF1
PEFB
PGB
36 64 x 36
Write
Pointer
Read
Pointer
B0 - B35
FF
AF
FS0
FS1
A0 - A35
PGA
PEFA
MBF2
Status Flag
Logic
FIFO
Programmable
Flag Offset
Registers
Parity
Gen/Check
Mail 2
Register
PPoorrtt--BB
CCoonnttrrooll
LLooggiicc
EF
AE
CLKB
CSB
W/RB
ENB
BE
SIZ0
SIZ1
SW0
SW1
3145 drw 01
The IDT logo is a registered trademark and SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
©1997 Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
MAY 1997
DSC-3145/4
1

1 page




IDT723613L20PF pdf
IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING
64 x 36
COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTION (CONTINUED)
Symbol
ODD/
EVEN
PEFA
PEFB
PGA
PGB
RST
SIZ0,
SIZ1
Name
Odd/Even Parity
Select
Port A Parity Error
Flag
Port B Parity Error
Flag
Port A Parity
Generation
Port B Parity
Reset
Port B Bus Size
Selects
I/O
I
O
(Port A)
O
(Port B)
I
I
I
I
(Port B)
Description
Odd parity is checked on each port when ODD/EVEN is HIGH, and even
parity is checked when ODD/EVEN is LOW. ODD/EVEN also selects the
type of parity generated for each port if parity generation is enabled for a read
operation.
When any byte applied to terminals A0-A35 fails parity, PEFA is LOW. Bytes
are organized as A0-A8, A9-A17, A18-A26, and A27-A35, with the most
significant bit of each byte serving as the parity bit. The type of parity
checked is determined by the state of the ODD/EVEN input.
The parity trees used to check the A0-A35 inputs are shared by the mail2
register to generate parity if parity generation is selected by PGA. Therefore, if
a mail2 read with parity generation is set up by having CSA LOW, ENA HIGH,
W/RA LOW, MBA HIGH and PGA HIGH, the PEFA flag is forced HIGH
regardless of the state of the A0-A35 inputs.
When any valid byte applied to terminals B0-B35 fails parity, PEFB is LOW.
Bytes are organized as B0-B8, B9-B17, B-18-B26, and B27-B35, with the
most significant bit of each byte serving as the parity bit. A byte is valid when
it is used by the bus size selected for port B. The type of parity checked is
determined by the state of the ODD/EVEN input.
The parity trees used to check the B0-B35 inputs are shared by the mail1
register to generate parity if parity generation is selected by PGB. Therefore, if
a mail1 read with parity generation is set up by having CSB LOW, ENB HIGH,
W/RB LOW, SIZ1 and SIZ0 HIGH and PGB HIGH, the PEFB flag is forced
HIGH regardless of the state of the B0-B35 inputs.
Parity is generated for data reads from the mail2 register when PGA is HIGH.
The type of parity generated is selected by the state of the ODD/EVEN input.
Bytes are organized at A0-A8, A9-A17, A18-A26, and A27-A35. The gener-
ated parity bits are output in the most significant bit of each byte.
Parity is generated for data reads from port B when PGB is HIGH. The type of
parity generated is selected by the state of the ODD/EVEN input. Bytes are
organized as B0-B8, B9-B17, B18-B26, and B27-B35. The generated parity
bits are output in the most significant bit of each byte.
To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-
HIGH transitions of CLKB must occur while RST is LOW. This sets the AF,
MBF1, and MBF2 flags HIGH and the EF, AE, and FF flags LOW. The LOW-
to-HIGH transition of RST latches the status of the FS1 and FS0 inputs to
select almost-full flag and almost-empty flag offset.
A LOW-to-HIGH transition of CLKB latches the states of SIZ0, SIZ1, and BE,
and the following LOW-to-HIGH transition of CLKB implements the latched
states as a port B bus size. Port B bus sizes can be long word, word, or byte.
A HIGH on both SIZ0 and SIZ1 accesses the mailbox registers for a port B 36-bit
write or read.
SW0,
SW1
W/RA
W/RB
Port B Byte Swap
Selects
Port A Write/Read
Select
Port B Write/Read
Select
I
(Port B)
I
I
At the beginning of each long word FIFO read, one of four modes of byte-
order swapping is selected by SW0 and SW1. The four modes are no swap,
byte swap, word swap, and byte-word swap. Byte-order swapping is possible
with any bus-size selection.
A HIGH selects a write operation and a LOW selects a read operation on
port A for a LOW-to-HIGH transition of CLKA. The A0-A35 outputs are in the
high-impedance state when W/RA is HIGH.
A HIGH selects a write operation and a LOW selects a read operation on
port B for a LOW-to-HIGH transition of CLKB. The B0-B35 outputs are in the
high-impedance state when W/RB is HIGH.
5

5 Page





IDT723613L20PF arduino
IDT723613 CMOS CLOCKED FIFO WITH BUS MATCHING AND BYTE SWAPPING
64 x 36
COMMERCIAL TEMPERATURE RANGES
empty+2. The almost-empty state is defined by the value of
the almost-full and almost-empty offset register (X). This
register is loaded with one of four preset values during a
device reset (see reset above). The almost-empty flag is LOW
when the FIFO contains X or less long words in memory and
is HIGH when the FIFO contains (X+1) or more long words.
Two LOW-to-HIGH transitions on the port B clock (CLKB)
are required after a FIFO write for the almost-empty flag to
reflect the new level of fill. Therefore, the almost-empty flag
of a FIFO containing (X+1) or more long words remains LOW
if two CLKB cycles have not elapsed since the write that filled
the memory to the (X+1) level. The almost-empty flag is set
HIGH by the second CLKB LOW-to-HIGH transition after the
FIFO write that fills memory to the (X+1) level. A LOW-to-
HIGH transition of CLKB begins the first synchronization cycle
if it occurs at time tSKEW2 or greater after the write that fills the
FIFO to (X+1) long words. Otherwise, the subsequent CLKB
cycle can be the first synchronization cycle (see Figure 11).
ALMOST FULL FLAG (AF)
The FIFO almost-full flag is synchronized to the port
clock that writes data to its array (CLKA). The state machine
that controls an almost-full flag monitors a write-pointer and
read-pointer comparator that indicates when the FIFO SRAM
status is almost full, almost full-1, or almost full-2. The almost-
full state is defined by the value of the almost-full and almost-
empty offset register (X). This register is loaded with one of
four preset values during a device reset (see reset above).
The almost-full flag is LOW when the FIFO contains (64-X) or
more long words in memory and is HIGH when the FIFO
contains [64-(X+1)] or less long words.
Two LOW-to-HIGH transitions on the port A clock (CLKA)
are required after a FIFO read for the almost-full flag to reflect
the new level of fill. Therefore, the almost-full flag of a FIFO
containing [64-(X+1)] or less words remains LOW if two CLKA
cycles have not elapsed since the read that reduced the
number of long words in memory to [64-(X+1)]. The almost-
full flag is set HIGH by the second CLKA LOW-to-HIGH
transition after the FIFO read that reduces the number of long
words in memory to [64-(X+1)]. A LOW-to-HIGH transition on
CLKA begins the first synchronization cycle if it occurs at time
tSKEW2 or greater after the read that reduces the number of
long words in memory to [64-(X+1)]. Otherwise, the subse-
quent CLKA cycle can be the first synchronization cycle (see
Figure 12).
MAILBOX REGISTERS
Two 36-bit bypass registers (mail1, mail2) are on the
IDT723613 to pass command and control information be-
tween port A and port B without putting it in queue. A LOW-to-
HIGH transition on CLKA writes A0-A35 data to the mail1
register when a port A write is selected by CSA, W/RA, and
ENA (with MBA HIGH). A LOW-to-HIGH transition on CLKB
writes B0-B35 data to the mail2 register when a port B write is
selected by CSB, W/RB, and ENB (and both SIZ0 and SIZ1
are HIGH). Writing data to a mail register sets its correspond-
ing flag (MBF1 or MBF2) LOW. Attempted writes to a mail
register are ignored while its mail flag is LOW.
When the port B data (B0-B35) outputs are active, the
data on the bus comes from the FIFO output register when
either one or both SIZ1 and SIZ0 are LOW and from the mail1
register when both SIZ1 and SIZ0 are HIGH. The mail1
register flag (MBF1) is set HIGH by a rising CLKB edge when
a port B read is selected by CSB, W/RB, and ENB, (and both
SIZ1 and SIZ0 HIGH). The mail2 register flag (MBF2) is set
HIGH by a rising CLKA edge when a port A read is selected
by CSA, W/RA, and ENA (with MBA HIGH). The data in a mail
register remains intact after it is read and changes only when
new data is written to the register.
DYNAMIC BUS SIZING
The port B bus can be configured in a 36-bit long word,
18-bit word, or 9-bit byte format for data read from the FIFO.
Word- and byte-size bus selections can utilize the most
significant bytes of the bus (big endian) or least significant
bytes of the bus (little endian). Port B bus-size can be
changed dynamically and synchronous to CLKB to commu-
nicate with peripherals of various bus widths.
The levels applied to the port B bus-size select (SIZ0,
SIZ1) inputs and the big-endian select (BE) input are stored
on each CLKB LOW-to-HIGH transition. The stored port B
bus-size selection is implemented by the next rising edge on
CLKB according to Figure 1.
Only 36-bit long-word data is written to or read from the
FIFO memory on the IDT723613. Bus-matching operations
are done after data is read from the FIFO RAM. Port B bus
sizing does not apply to mail register operations.
BUS-MATCHING FIFO READS
Data is read from the FIFO RAM in 36-bit long-word
increments. If a long-word bus-size is implemented, the entire
long word immediately shifts to the FIFO output register upon
a read. If byte or word size is implemented on port B, only the
first one or two bytes appear on the selected portion of the FIFO
output register, with the rest of the long word stored in auxiliary
registers. In this case, subsequent FIFO reads with the same
bus-size implementation output the rest of the long word to the
FIFO output register in the order shown by Figure 1.
Each FIFO read with a new bus-size implementation
automatically unloads data from the FIFO RAM to its output
register and auxiliary registers. Therefore, implementing a
new port B bus-size and performing a FIFO read before all
bytes or words stored in the auxiliary registers have been read
results in a loss of the unread data in these registers.
When reading data from FIFO in byte or word format, the
unused B0-B35 outputs remain inactive but static, with the
unused FIFO output register bits holding the last data value to
decrease power consumption.
BYTE SWAPPING
The byte-order arrangement of data read from the FIFO
can be changed synchronous to the rising edge of CLKB.
Byte-order swapping is not available for mail register data.
Four modes of byte-order swapping (including no swap) can
be done with any data port size selection. The order of the
bytes are rearranged within the long word, but the bit order
within the bytes remaines constant.
11

11 Page







PáginasTotal 29 Páginas
PDF Descargar[ Datasheet IDT723613L20PF.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
IDT723613L20PFCMOS Clocked FIFO With Bus Matching and Byte Swapping 64 x 36Integrated Device Technology
Integrated Device Technology
IDT723613L20PQFCMOS Clocked FIFO With Bus Matching and Byte Swapping 64 x 36Integrated Device Technology
Integrated Device Technology

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar