PDF IDT72265 Data sheet ( Hoja de datos )

Número de pieza	IDT72265
Descripción	CMOS SUPERSYNC FIFOO 8/192 x 18/ 16/384 x 18
Fabricantes	Integrated Device Technology
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No Preview Available ! CMOS SUPERSYNC FIFO™ 8,192 x 18, 16,384 x 18 IDT72255 IDT72265 Integrated Device Technology, Inc. FEATURES: • 8,192 x 18-bit storage capacity (IDT72255) • 16,384 x 18-bit storage capacity (IDT72265) • 10ns read/write cycle time (8ns access time) • Retransmit Capability • Auto power down reduces power consumption • Master Reset clears entire FIFO, Partial Reset clears data, but retains programmable settings • Empty, Full and Half-full flags signal FIFO status • Programmable Almost Empty and Almost Full flags, each flag can default to one of two preselected offsets • Program partial flags by either serial or parallel means • Select IDT Standard timing (using EF and FF flags) or First Word Fall Through timing (using OR and IR flags) • Easily expandable in depth and width • Independent read and write clocks (permit simultaneous reading and writing with one clock signal) • Available in the 64-pin Thin Quad Flat Pack (TQFP), 64- pin Slim Thin Quad Flat Pack (STQFP) and the 68-pin Pin Grid Array (PGA) • Output enable puts data outputs into high impedance • High-performance submicron CMOS technology • Industrial temperature range (-40oC to +85oC) is avail- able, tested to military electrical specifications DESCRIPTION: The IDT72255/72265 are monolithic, CMOS, high capac- ity, high speed, low power First-In, First-Out (FIFO) memories with clocked read and write controls. These FIFOs are appli- cable for a wide variety of data buffering needs, such as optical disk controllers, local area networks (LANs), and inter-proces- sor communication. Both FIFOs have an 18-bit input port (Dn) and an 18-bit output port (Qn). The input port is controlled by a free-running clock (WCLK) and a data input enable pin (WEN). Data is written into the synchronous FIFO on every clock when WEN is asserted. The output port is controlled by another clock pin (RCLK) and enable pin (REN). The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronously for dual clock operation. An output enable pin (OE) is provided on the read port for three-state control of the outputs. The IDT72255/72265 have two modes of operation: In the IDT Standard Mode, the first word written to the FIFO is deposited into the memory array. A read operation is required to access that word. In the First Word Fall Through Mode (FWFT), the first word written to an empty FIFO appears FUNCTIONAL BLOCK DIAGRAM WEN WCLK D0-D17 LD SEN • • WRITE CONTROL LOGIC WRITE POINTER INPUT REGISTER •• RAM ARRAY 8,192 x 18 16,384 x 18 •• MRS PRS FS RESET LOGIC TIMING OUTPUT REGISTER • OE Q0-Q17 OFFSET REGISTER FLAG LOGIC READ POINTER FF/IR PAF EF/OR HPAF E FWFT/SI READ CONTROL LOGIC RT • RCLK • REN 3037 drw 01 SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES ©1997 Integrated Device Technology, Inc For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391. MAY 1997 DSC-3037/7 1 1 page IDT72255/72265 SyncFIFO™ 8,192 x 18, 16,384 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES ABSOLUTE MAXIMUM RATINGS(1) Symbol Rating Commercial Military Unit VTERM Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V with respect to GND TA Operating Temperature 0 to +70 –55 to +125 °C TBIAS Temperature Under –55 to +125 –65 to +135 °C Bias TSTG Storage Temperature –55 to +125 –65 to +155 °C IOUT DC Output Current 50 50 mA NOTE: 3037 tbl 02 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT- INGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maimum rating conditions for extended periods may affect reliabilty. RECOMMENDED DC OPERATING CONDITIONS Symbol VCCM VCCC Parameter Military Supply Voltage Commercial Supply Voltage Min. Typ. Max. Unit 4.5 5.0 5.5 V 4.5 5.0 5.5 V GND Supply Voltage 0 0 0V VIH Input High Voltage 2.0 — — V Commercial VIH Input High Voltage 2.2 — — V Military VIL(1) Input Low Voltage — — 0.8 V Commercial & Military NOTE: 3037 tbl 03 1. 1.5V undershoots are allowed for 10ns once per cycle. DC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C) Symbol Parameter ILI(1) Input Leakage Current (any input) ILO(2) Output Leakage Current VOH Output Logic “1” Voltage, IOH = –2 mA VOL Output Logic “0” Voltage, IOL = 8 mA ICC1(3) Active Power Supply Current ICC2(3,4) Power Down Current (All inputs = VCC - 0.2V or GND + 0.2V, RCLK and WCLK are free-running) NOTES: 1. Measurements with 0.4 ≤ VIN ≤ VCC. 2. OE = VIH 3. Tested at f = 20 MHz with outputs unloaded. 4. No data written or read for more than 10 cycles DT72255L IDT72265L Commercial tCLK = 10, 12,15, 20ns Min. Typ. Max. –1 — 1 –10 — 10 2.4 — — — — 0.4 — — 180 — — 15 IDT72255L IDT72265L Military tCLK = 15, 25ns Min. Typ. Max. –10 — 10 –10 — 10 2.4 — — — — 0.4 — — 250 — — 25 Unit µA µA V V mA mA 3037 tbl 04 CAPACITANCE (TA = +25°C, f = 1.0MHz) Symbol Parameter(1) Conditions Max. CIN(2) COUT(1,2) Input Capacitance Output Capacitance VIN = 0V VOUT = 0V 10 10 NOTES: 1. With output deselected, (OE=HIGH). 2. Characterized values, not currently tested. Unit pF pF 3037 tbl 05 5 5 Page IDT72255/72265 SyncFIFO™ 8,192 x 18, 16,384 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES OUTPUTS: FULL FLAG (FF/IR) This is a dual purpose pin. In IDT Standard Mode, the Full Flag (FF) function is selected. When the FIFO is full (i.e. the write pointer catches up to the read pointer), FF will go LOW, inhibiting further write operation. When FF is HIGH, the FIFO is not full. If no reads are performed after a reset (either MRS or PRS), FF will go LOW after 8,192 writes tor the IDT72255 and 16,384 writes to the IDT72265. In FWFT Mode, the Input Ready (IR) function is selected. IR goes LOW when memory space is available for writing in data. When there is no longer any free space left, IR goes HIGH, inhibiting further write operation. If no reads are performed after a reset (either MRS or PRS), IR will go HIGH after 8,193 writes for the IDT72255 and 16,385 writes for the IDT72265. The IR status not only measures the contents of the FIFO memory, but also counts the presence of a word in the output register. Thus, in FWFT mode, the total number of writes necessary to deassert IR is one greater than needed to assert FF in IDT Standard mode. FF/IR is synchronized to WCLK. It is double-registered to enhance metastable immunity. EMPTY FLAG (EF/OR) This is a dual purpose pin. In the IDT Standard Mode, the Empty Flag (EF) function is selected. When the FIFO is empty (i.e. the read pointer catches up to the write pointer), EF will go LOW, inhibiting further read operations. When EF is HIGH, the FIFO is not empty. When writing the first word to an empty FIFO, the deassertion time of EF is variable, and can be represent by the First Word Latency parameter, tFWL1, which is measured from the rising WCLK edge that writes the first word to the rising RCLK edge that updates the flag. tFWL1 includes any delays due to clock skew and can be expressed as follows: tFWL1 max. = 10Tf + 2TRCLK (in ns) where Tf is either the RCLK or the WCLK period, whichever is shorter, and TRCLK is the RCLK period. Since no read can take place until EF goes HIGH, the tFWL1 delay determines how early the first word can be available at Qn. This delay has no effect on the reading of subsequent words. In FWFT Mode, the Ouput Ready (OR) function is selected. OR goes LOW at the same time that the first word written to an empty FIFO appears valid on the outputs. OR goes HIGH one cycle after RCLK shifts the last word from the FIFO memory to the outputs. Then further data reads are inhibited until OR goes LOW again. When writing the first word to an empty FIFO, the assertion time of OR is variable, and can be represented by the First Word Latency parameter, tFWL2, which is measured from the rising WCLK edge that writes the first word to the rising RCLK edge that updates the flag. tFWL2 includes any delay due to clock skew and can be expressed as follows: tFWL2 max. = 10Tf + 3TRCLK (in ns) where Tf is either the RCLK or the WCLK period, whichever is shorter, and TRCLK is the RCLK period. Note that the First Word Latency in FWFT mode is one RCLK cycle longer than in IDT Standard mode. The tFWL2 delay determines how early the first word can be available at Qn. This delay has no effect on the reading of subsequent words. EF/OR is sychronized to the RCLK. It is double-registered to enhance metastable immunity. 72255 – 8,192 x 18–BIT 17 12 0 17 72265 – 16,384 x 18–BIT 13 0 EMPTY OFFSET REGISTER DEFAULT VALUE 07FH if LD is LOW at Master Reset, 3FFH if LD is HIGH at Master Reset EMPTY OFFSET REGISTER DEFAULT VALUE 07FH if LD is LOW at Master Reset, 3FFH if LD is HIGH at Master Reset 17 12 0 17 13 0 FULL OFFSET REGISTER DEFAULT VALUE 07FH if LD is LOW at Master Reset, 3FFH if LD is HIGH at Master Reset NOTE: 3037 drw 05 1. Any bits of the offset register not being programmed should be set to zero. FULL OFFSET REGISTER DEFAULT VALUE 07FH if LD is LOW at Master Reset, 3FFH if LD is HIGH at Master Reset 3037 drw 06 Figure 3. Offset Register Location and Default Values 11 11 Page

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