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PDF IDT72264 Data sheet ( Hoja de datos )

Número de pieza IDT72264
Descripción VARIABLE WIDTH SUPERSYNCO FIFO 8/192 x 18 or 16/384 x 9 16/384 x 18 or 32/768 x 9
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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VARIABLE WIDTH SUPERSYNCFIFO
8,192 x 18 or 16,384 x 9
16,384 x 18 or 32,768 x 9
IDT72264
IDT72274
Integrated Device Technology, Inc.
FEATURES:
• Select 8192 x 18 or 16384x 9 organization (IDT72264)
• Select 16384 x 18 or 32678 x 9 organization (IDT72274)
• Flexible control of read and write clock frequencies
• Reduced dynamic power dissipation
• Auto power down minimizes power consumption
• 15 ns read/write cycle time (10 ns access time)
• Retransmit Capability
• Master Reset clears entire FIFO, Partial Reset clears
data, but retains programmable settings
• Empty, full and half-full flags signal FIFO status
• Programmable almost empty and almost full flags, each
flag can default to one of two preselected offsets
• Program partial flags by either serial or parallel means
• Select IDT Standard timing (using EF and FF flags) or
First Word Fall Through timing (using OR and IR flags)
• Easily expandable in depth and width
• Independent read and write clocks (permits simultaneous
reading and writing with one clock signal)
• Available in the 64-pin Thin Quad Flat Pack (TQFP), 64-
pin Slim Thin Quad Flat Pack (STQFP) and the 68-pin
Pin Grid Array (PGA)
• Output enable puts data outputs into high impedance
• High-performance submicron CMOS technology
FUNCTIONAL BLOCK DIAGRAM
• Industrial temperature range (-40OC to +85OC) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT72264/72274 are monolithic, CMOS, high capac-
ity, high speed, low power first-in, first-out (FIFO) memories
with clocked read and write controls. These FIFOs have three
main features that distinguish them among SuperSync FIFOs:
First, the data path width can be changed from 9-bits to 18-
bits; as a result, halving the depth. A pin called Memory Array
Select (MAC) chooses between the two options. This feature
helps reduce the need for redesigns or multiple versions of PC
cards, since a single layout can be used for both data bus
widths.
Second, IDT72264/72274 offer the greatest flexibility for
setting and varying the read and write clock (WCLK and
RCLK) frequencies. For example, given that the two clock
frequencies are unequal, the slower clock may exceed the
faster by, at most, twice its frequency. This feature is espe-
cially useful for communications and network applications
where clock frequencies are switched to permit different data
rates.
WEN WCLK
D0-Dn
LD SEN
••
INPUT REGISTER
OFFSET REGISTER
WRITE CONTROL
LOGIC
WRITE POINTER
MAC
MEMORY ARRAY
CONFIGURATION
••
RAM ARRAY
8192 x 18 or 16384 x 9
16384 x 18 or 32768 x 9
••
OUTPUT REGISTER
FLAG
LOGIC
READ POINTER
FPFA/FIR
EF/OR
PAE
HF
FWFT/SI
READ
CONTROL
LOGIC
RT
MRS
RESET
PRS LOGIC
RCLK
REN
FS TIMING
OE Q0-Qn
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGES
3218 drw 01
©1997 Integrated Device Technology, Inc
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
MAY 1997
DSC-3218/2
1

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IDT72264 pdf
IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO
(8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9)
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Commercial Unit
VTERM
Terminal Voltage –0.5 to +7.0
with respect to GND
V
TA
Operating
0 to +70
°C
Temperature
TBIAS
Temperature Under –55 to +125
Bias
°C
TSTG
Storage
Temperature
–55 to +125
°C
IOUT
DC Output Current
50
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied.
Exposure to absolute maimum rating conditions for extended periods may
affect reliabilty.
COMMERCIAL TEMPERATURE RANGES
RECOMMENDED DC
OPERATING CONDITIONS
Symbol
V
CCC
Parameter
Commercial Supply
Voltage
Min. Typ. Max. Unit
4.5 5.0 5.5 V
GND Supply Voltage
0 0 0V
V
IH
V (1,2)
IL
Input High Voltage
Commercial
Input Low Voltage
Commercial
2.0 — — V
— — 0.8 V
NOTE:
1. Does not apply to MAC which can only be tied to Vcc or GND.
2. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C)
Symbol
Parameter
I (1)
LI
I (2)
LO
VOH
VOL
I (3)
CC1
Input Leakage Current (any input except MAC)
Output Leakage Current
Output Logic "1" Voltage, IOH = -2mA
Output Logic "0" Voltage, IOL = 8mA
Active Power Supply Current
MAS = VCC
MAS = GND
I (3,4)
CC2
Power Down Current (All inputs = VCC - 0.2V or
GND + 0.2V, RCLK and WCLK are free-running)
NOTES:
1.
2.
Measurements
OE + VIH
with
0.4
<
VIN
<
VCC.
3. Tested at f = 20 MHz with outputs uploaded.
4. No data written or read for more than 10 cycles.
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol Parameter(1) Conditions
Max.
CIN(2)
Input
Capacitance
VIN = 0V
10
COUT(1,2) Output
Capacitance
VOUT = 0V
10
Unit
pF
pF
NOTES:
1. With output deselected, (OE=HIGH).
2. Characterized values, not currently tested.
IDT72264L
IDT72274L
Commercial
tCLK = 15, 20ns
Min. Type
Max
-1 —
1
-10 —
10
2.4 —
— — 0.4
— — 115
— — 135
— — 115
Unit
µA
µA
V
V
mA
mA
mA
5

5 Page





IDT72264 arduino
IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO
(8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9)
COMMERCIAL TEMPERATURE RANGES
LD LOW and deactivate SEN or to set SEN LOW and deacti-
vate LD. Once LD and SEN are both restored to a LOW level,
serial offset programming continues from where it left off.
Note that the status of a partial flag (PAE or PAF) output is
invalid during the programming process. From the time
parallel programming has begun, a partial flag output will not
be valid until the appropriate offset word has been written to
the register(s) pertaining to that flag. From the time serial
programming has begun, neither partial flag will be valid until
the full set of bits required to fill all the offset registers has been
written. Measuring from the rising WCLK edge that achieves
either of the above criteria; PAF will be valid after two more
rising WCLK edges plus tPAF, PAE will be valid after the next
two rising RCLK edges plus tPAE (Add one more RCLK cycle
if tSKEW2 is not met.)
The act of reading the offset registers employs a dedicated
read offset register pointer. The contents of the offset regis-
ters can be read on the output lines when LD is set LOW and
72264 with MAC = GND (8,192 x 18–BIT)
17 12
0
72274 with MAC = GND (16,384 x 18–BIT)
17 13
0
EMPTY OFFSET REGISTER
DEFAULT VALUE
07FH if LD is LOW at Master Reset,
3FFH if LD is HIGH at Master Reset
EMPTY OFFSET REGISTER
DEFAULT VALUE
07FH if LD is LOW at Master Reset,
3FFH if LD is HIGH at Master Reset
17 12
0 17
13
0
FULL OFFSET REGISTER
DEFAULT VALUE
07FH if LD is LOW at Master Reset,
3FFH if LD is HIGH at Master Reset
3218 drw 05a
FULL OFFSET REGISTER
DEFAULT VALUE
07FH if LD is LOW at Master Reset,
3FFH if LD is HIGH at Master Reset
3218 drw 06a
72264 with MAC = Vcc (16,384 x 9–BIT)
72274 with MAC = Vcc (32,768 x 9–BIT)
87
08
7
0
EMPTY OFFSET (LSB) REG.
EMPTY OFFSET (LSB) REG.
DEFAULT VALUE
07FH if LD is LOW at Master Reset
3FFH if LD is HIGH at Master Reset
DEFAULT VALUE
07FH if LD is LOW at Master Reset
3FFH if LD is HIGH at Master Reset
85
08
6
0
EMPTY OFFSET (MSB) REG.
EMPTY OFFSET (MSB) REG.
00H 00H
87
08
7
0
FULL OFFSET (LSB) REG.
FULL OFFSET (LSB) REG.
DEFAULT VALUE
07FH if LD is LOW at Master Reset
3FFH if LD is HIGH at Master Reset
DEFAULT VALUE
07FH if LD is LOW at Master Reset
3FFH if LD is HIGH at Master Reset
85
08
6
FULL OFFSET (MSB) REG.
FULL OFFSET (MSB) REG.
00H 00H
NOTE:
3218 drw 05b
1. Any bits of the offset register not being programmed should be set to zero.
Figure 3. Offset Register Location and Default Values
0
3218 drw 06b
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