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PDF IDT72215 Data sheet ( Hoja de datos )
| Número de pieza | IDT72215 | |
| Descripción | CMOS SyncFIFOO 256 x 18/ 512 x 18/ 1024 x 18/ 2048 x 18 and 4096 x 18 | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de IDT72215 (archivo pdf) en la parte inferior de esta página. Total 21 Páginas | ||
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Integrated Device Technology, Inc.
CMOS SyncFIFO™
256 x 18, 512 x 18, 1024 x 18, 2048 x
18 and 4096 x 18
IDT72205LB
IDT72215LB
IDT72225LB
IDT72235LB
IDT72245LB
FEATURES:
• 256 x 18-bit organization array (72205LB)
• 512 x 18-bit organization array (72215LB)
• 1024 x 18-bit organization array (72225LB)
• 2048 x 18-bit organization array (72235LB)
• 4096 x 18-bit organization array (72245LB)
• 15 ns read/write cycle time
• Easily expandable in depth and width
• Read and write clocks can be asynchronous or coincident
• Dual-Port zero fall-through time architecture
• Programmable almost-empty and almost-full flags
• Empty and Full flags signal FIFO status
• Half-Full flag capability in a single device configuration
• Output enable puts output data bus in high-impedance
state
• High-performance submicron CMOS technology
• Available in a 64-lead thin quad flatpack (TQFP/STQFP),
pin grid array (PGA), and plastic leaded chip carrier
(PLCC)
• Military product compliant to MIL-STD-883, Class B
• Industrial temperature range (-40OC to +85OC) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT72205LB/72215LB/72225LB/72235LB/72245LB
are very high-speed, low-power First-In, First-Out (FIFO)
memories with clocked read and write controls. These FIFOs
are applicable for a wide variety of data buffering needs, such
as optical disk controllers, Local Area Networks (LANs), and
interprocessor communication.
Both FIFOs have 18-bit input and output ports. The input
port is controlled by a free-running clock (WCLK), and a data
input enable pin (WEN). Data is read into the synchronous
FIFO on every clock when WEN is asserted. The output port
is controlled by another clock pin (RCLK) and another enable
pin (REN). The read clock can be tied to the write clock for
single clock operation or the two clocks can run asynchronous
of one another for dual-clock operation. An Output Enable pin
(OE) is provided on the read port for three-state control of the
output.
The synchronous FIFOs have two fixed flags, Empty (EF)
and Full (FF), and two programmable flags, Almost-Empty
(PAE) and Almost-Full (PAF). The offset loading of the pro-
grammable flags is controlled by a simple state machine, and
is initiated by asserting the Load pin (LD). A Half-Full flag (HF)
is available when the FIFO is used in a single device configu-
ration.
The IDT72205LB/72215LB/72225LB/72235LB/72245LB
are depth expandable using a daisy-chain technique. The XI
and XO pins are used to expand the FIFOs. In depth expan-
sion configuration, FL is grounded on the first device and set
to HIGH for all other devices in the daisy chain.
The IDT72205LB/72215LB/72225LB/72235LB/72245LB is
fabricated using IDT’s high-speed submicron CMOS technol-
ogy. Military grade product is manufactured in compliance
with the latest revision of MIL-STD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
WCLK
WEN
D0-D17
LD
FL
(HF)/WWRXXXOII
RXO
RS
WRITE CONTROL
LOGIC
WRITE POINTER
EXPANSION LOGIC
RESET LOGIC
INPUT REGISTER
••
RAM ARRAY
256 x 18, 512 x 18
1024 x 18, 2048 x 18
4096 x 18
••
OUTPUT REGISTER
OFFSET REGISTER
FLAG
LOGIC
READ POINTER
READ CONTROL
LOGIC
PHFPEFAFAF/EF(WXO)
OE Q0-Q17
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc
RCLK
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
5.16
REN
2766 drw 01
DECEMBER 1996
DSC-2766/7
1
1 page  
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™
256 x 18-BIT, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Rating
Commercial MIilitary Unit
VTERM Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V
with respect to GND
TA Operating
Temperature
0 to +70 –55 to +125 °C
TBIAS
Temperature Under –55 to +125 –65 to +135 °C
Bias
TSTG
Storage
Temperature
–55 to +125 –65 to +155 °C
IOUT DC Output Current
50
50 mA
NOTE:
2766 tbl 02
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-
INGS may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maimum rating conditions for extended
RECOMMENDED DC
OPERATING CONDITIONS
Symbol
VCCM
VCCC
Parameter
Military Supply
Voltage
Commercial Supply
Voltage
Min.
4.5
4.5
GND Supply Voltage
0
VIH
VIH
VIL(1)
Input High Voltage
Commercial
Input High Voltage
Military
Input Low Voltage
Commercial & Military
2.0
2.2
—
Typ.
5.0
5.0
0
—
—
—
Max.
5.5
5.5
0
—
—
0.8
Unit
V
V
V
V
V
V
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
2766 tbl 03
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)
IDT72205LB
IDT72215LB
IDT72225LB
Commercial
tCLK = 15, 20, 25, 35, 50ns
IDT72205LB
IDT72215LB
IDT72225LB
Military
tCLK = 25, 35, 50ns
Symbol
Parameter
Min. Typ. Max. Min. Typ. Max.
ILI(1)
Input Leakage Current (any input)
–1 —
1 –10 — 10
ILO(2) Output Leakage Current
–10 —
10 –10
— 10
VOH Output Logic “1” Voltage, IOH = –2 mA
2.4 —
— 2.4
——
VOL
Output Logic “0” Voltage, IOL = 8 mA
—
—
0.4 —
— 0.4
ICC1(3) Active Power Supply Current
— — 200 — — 250
ICC2(3) Average Standby Current (All Input = VCC – 0.2V,
—
—
70 —
— 85
except RCLK and WCLK which are free-running)
Unit
µA
µA
V
V
mA
mA
IDT72235LB
IDT72245LB
Commercial
tCLK = 15, 20, 25, 35, 50ns
Symbol
Parameter
ILI(1) Input Leakage Current (any input)
ILO(2)
Output Leakage Current
VOH Output Logic “1” Voltage, IOH = –2 mA
VOL
ICC1(4)
ICC2(4)
Output Logic “0” Voltage, IOL = 8 mA
Active Power Supply Current
Average Standby Current (All Input = VCC – 0.2V,
except RCLK and WCLK which are free-running)
NOTES:
1. Measurements with 0.4 ≤ VIN ≤ VCC.
2. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
3 & 4. Tested at f = 20MHz with outputs unloaded.
(3) Typical Icc1 = 60 + (fCLK*0.57/MHz) + (fCLK*CL*0.02/MHz-pF) mA
(4 ) Typical Icc1 = 80 + (fCLK + 0.73/MHz) + (fCLK*CL*0.02/MHz-pF) mA
fCLK = 1/tCLK, CL = external capacitive load (30 pF typical)
Min.
–1
–10
2.4
—
—
—
Typ.
—
—
—
—
—
—
Max.
1
10
—
0.4
200
70
IDT72235LB
IDT72245LB
Military
tCLK = 25, 35, 50ns
Min. Typ. Max.
–10 —
10
–10 —
10
2.4 —
—
— — 0.4
— — 250
— — 85
Unit
µA
µA
V
V
mA
mA
2766 tbl 04
5.16 5
5 Page 
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFO™
256 x 18-BIT, 512 x 18, 1024 x 18, 2048 x 18 and 4096 x 18
RCLK
REN
EF
Q0 - Q17
OE
WCLK
t CLKH
t CLK
t CLKL
t
ENS
tENH
NO OPERATION
tREF
tA
t OLZ
t OE
t
(1)
SKEW2
MILITARY AND COMMERCIAL TEMPERATURE RANGES
t REF
VALID DATA
t OHZ
WEN
2766 drw 09
NOTE:
1. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. If the
time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK edge.
Figure 7. Read Cycle Timing
5.16 11
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet IDT72215.PDF ] | |
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