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PDF IDT72201 Data sheet ( Hoja de datos )

Número de pieza IDT72201
Descripción CMOS SyncFIFOO 64 X 9/ 256 x 9/ 512 x 9/ 1024 X 9/ 2048 X 9 and 4096 x 9
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9CMOS SyncFIFO
IDT72421MILITARY AND COMMERCIAL TEMPERATURE RANGES
64 X 9, 256 x 9, 512 x 9,
IDT72201
IDT72211
1024 X 9, 2048 X 9 and 4096 x 9
IDT72221
IDT72231
Integrated Device Technology, Inc.
IDT72241
FEATURES:
• 64 x 9-bit organization (IDT72421)
• 256 x 9-bit organization (IDT72201)
• 512 x 9-bit organization (IDT72211)
• 1024 x 9-bit organization (IDT72221)
• 2048 x 9-bit organization (IDT72231)
• 4096 x 9-bit organization (IDT72241)
• 12 ns read/write cycle time (IDT72421/72201/72211)
• 15 ns read/write cycle time (IDT72221/72231/72241)
• Read and write clocks can be independent
• Dual-Ported zero fall-through time architecture
• Empty and Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags can
be set to any depth
• Programmable Almost-Empty and Almost-Full flags
default to Empty+7, and Full-7, respectively
• Output enable puts output data bus in high-impedance
state
• Advanced submicron CMOS technology
• Available in 32-pin plastic leaded chip carrier (PLCC),
ceramic leadless chip carrier (LCC), and 32-pin Thin
Quad Flat Pack (TQFP)
• For Through-Hole product please see the IDT72420/
72200/72210/72220/72230/72240 data sheet
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT72421/72201/72211/72221/72231/72241
SyncFIFOare very high-speed, low-power First-In, First-
Out (FIFO) memories with clocked read and write controls.
The IDT72421/72201/72211/72221/72231/72241 have a 64,
256, 512, 1024, 2048, and 4096 x 9-bit memory array,
respectively. These FIFOs are applicable for a wide variety of
data buffering needs such as graphics, local area networks
and interprocessor communication.
These FIFOs have 9-bit input and output ports. The input
port is controlled by a free-running clock (WCLK), and two
write enable pins (WEN1, WEN2). Data is written into the
Synchronous FIFO on every rising clock edge when the write
enable pins are asserted. The output port is controlled by
another clock pin (RCLK) and two read enable pins (REN1,
REN2). The read clock can be tied to the write clock for single
clock operation or the two clocks can run asynchronous of one
another for dual-clock operation. An output enable pin (OE) is
provided on the read port for three-state control of the output.
The Synchronous FIFOs have two fixed flags, Empty (EF)
and Full (FF). Two programmable flags, Almost-Empty (PAE)
and Almost-Full (PAF), are provided for improved system
control. The programmable flags default to Empty+7 and Full-
7 for PAE and PAF, respectively. The programmable flag
offset loading is controlled by a simple state machine and is
initiated by asserting the load pin (LD).
The IDT72421/72201/72211/72221/72231/72241 are
fabricated using IDT’s high-speed submicron CMOS
technology. Military grade product is manufactured in
compliance with the latest revision of MIL-STD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
WCLK
WEN1
WEN2
WRITE CONTROL
LOGIC
WRITE POINTER
D0 - D8
INPUT REGISTER
RAM ARRAY
64 x 9, 256 x 9,
512 x 9, 1024 x 9,
2048 x 9, 4096 x 9
LD
OFFSET REGISTER
FLAG
LOGIC
READ POINTER
READ CONTROL
LOGIC
EF
PAE
PAF
FF
RESET LOGIC
OUTPUT REGISTER
RS
OE Q0 - Q8
SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391. 5.07
RCLK
REN1
REN2
2655 drw 01
DECEMBER 1995
DSC-2655/6
1

1 page




IDT72201 pdf
IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)
Commercial
Commercial and Military
72221L15 72221L20 72221L25 72221L35 72221L50
72231L15 72231L20 72231L25 72231L35 72231L50
72241L15 72241L20 72241L25 72241L35 72241L50
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
fS Clock Cycle Frequency
— 66.7 — 50 — 40 — 28.6 — 20 MHz
tA Data Access Time
2 10 2 12 3 15 3 20 3 25 ns
tCLK Clock Cycle Time
15 — 20 — 25 — 35 — 50 — ns
tCLKH Clock HIGH Time
6 — 8 — 10 — 14 — 20 — ns
tCLKL Clock LOW Time
6 — 8 — 10 — 14 — 20 — ns
tDS Data Set-up Time
4 — 5 — 6 — 8 — 10 — ns
tDH Data Hold Time
1 — 1 — 1 — 2 — 2 — ns
tENS Enable Set-up Time
4 — 5 — 6 — 8 — 10 — ns
tENH
tRS
Enable Hold Time
Reset Pulse Width(1)
1 —1—
15 — 20 —
1 — 2 — 2—
25 — 35 — 50 —
ns
ns
tRSS Reset Set-up Time
15 — 20 — 25 — 35 — 50 — ns
tRSR Reset Recovery Time
15 — 20 — 25 — 35 — 50 — ns
tRSF Reset to Flag Time and Output Time
— 15 — 20 — 25 — 35 — 50 ns
tOLZ Output Enable to Output in Low-Z(2)
0 — 0 — 0 — 0 — 0 — ns
tOE
tOHZ
Output Enable to Output Valid
Output Enable to Output in High-Z(2)
3 8 3 10 3 13 3 15 3 28 ns
3 8 3 10 3 13 3 15 3 28 ns
tWFF Write Clock to Full Flag
— 10 — 12 — 15 — 20 — 30 ns
tREF Read Clock to Empty Flag
— 10 — 12 — 15 — 20 — 30 ns
tPAF Write Clock to Programmable Almost-Full Flag
— 10 — 12 — 15 — 20 — 30 ns
tPAE Read Clock to Programmable Almost-Empty Flag
— 10 — 12 — 15 — 20 — 30 ns
tSKEW1 Skew Time Between Read Clock and Write Clock
for Empty Flag and Full Flag
6 — 8 — 10 — 12 — 15 — ns
tSKEW2 Skew Time Between Read Clock and Write Clock
for Programmable Almost-Empty Flag and
Programmable Almost-Full Flag
28 — 35 — 40 — 42 — 45 — ns
NOTES:
1. Pulse widths less than minimum values are not allowed.
2. Values guaranteed by design, not currently tested.
2655 tbl 08
AC TEST CONDITIONS
In Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1
2655 tbl 09
D.U.T.
680
5V
1.1K
30pF*
2655 drw 03
or equivalent circuit
Figure 1. Output Load
*Includes jig and scope capacitances.
5.07 5

5 Page





IDT72201 arduino
IDT72421/72201/72211/72221/72231/72241 CMOS SyncFIFO
64 x 9, 256 x 9, 512 x 9, 1024 x 9, 2048 x 9 and 4096 x 9
RCLK
tCLKH
tCLK
tCLKL
REN1,
REN2
EF
tENS
tENH
tREF
NO OPERATION
tA
Q0 - Q8
OE
WCLK
tOLZ
tOE
VALID DATA
tOHZ
tSKEW1 (1)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
tREF
WEN1
WEN2
2655 drw 08
NOTE:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for EF to change during the current clock cycle. If the time between
the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then EF may not change state until the next RCLK edge. Figure 6. Read Cycle
Timing
Figure 6. Read Cycle Timing
5.07 11

11 Page







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