PDF IDT72132 Data sheet ( Hoja de datos )

Número de pieza	IDT72132
Descripción	CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 4096 x 9
Fabricantes	Integrated Device Technology
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No Preview Available ! Integrated Device Technology, Inc. CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 4096 x 9 IDT72132 IDT72142 FEATURES: • 35ns parallel-port access time, 45ns cycle time • 50MHz serial port shift rate • Expandable in depth and width with no external components • Programmable word lengths including 8, 9, 16-18, and 32-36 bit using Flexshift™ serial input without using any additional components • Multiple status flags: Full, Almost-Full (1/8 from full), Half-Full, Almost Empty (1/8 from empty), and Empty • Asynchronous and simultaneous read and write operations • Dual-Port zero fall-through architecture • Retransmit capability in single device mode • Produced with high-performance, low-power CMOS technology • Available in the 28-pin plastic DIP • Industrial temperature range (-40oC to +85oC) is avail- able, tested to military electrical specifications DESCRIPTION: The IDT72132/72142 are high-speed, low-power serial-to- parallel FIFOs. These FIFOs are ideally suited to serial communications applications, tape/disk controllers, and local area networks (LANs). The IDT72132/72142 can be config- ured with the IDTs parallel-to-serial FIFOs (IDT72131/72141) for bidirectional serial data buffering. The FIFO has a serial input port and a 9-bit parallel output port. Wider and deeper serial-to-parallel data buffers can be NWbuilt using multiple IDT72132/72142 chips. IDTs unique Flexshift serial expansion logic (SIX, ) makes width expansion possible with no additional components. These FIFOs will expand to a variety of word widths including 8, 9, 16, and 32 bits. The IDT72132/142 can also be directly connected for depth expansion. Five flags are provided to monitor the FIFO. The full and empty flags prevent any FIFO data overflow or underflow conditions. The Almost-Full (7/8), Half-Full, and Almost Empty (1/8) flags signal memory utilization within the FIFO. The IDT72132/72142 is fabricated using IDTs high-speed submicron CMOS technology. FUNCTIONAL BLOCK DIAGRAM SICP SIX SI D7 D8 SERIAL INPUT CIRCUITRY NW NEXT WRITE POINTER RAM ARRAY 2048 x 9 4096 x 9 RS FL/RT RESET LOGIC XI EXPANSION LOGIC XO/ OE Q0-Q 8 PIN CONFIGURATION FLAG LOGIC READ POINTER EF AEF /HF FF R NW GND XI AEF FF Q0 Q1 Q2 Q3 Q4 GND R Q5 Q6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 P28-1 & C28-3 28 Vcc 27 D7 26 D8 25 FL/RT 24 RS 23 SI 22 SICP 21 SIX 20 OE 19 EF 18 XO/HF 17 GND 16 Q8 15 Q7 2752 drw 01 DIP TOP VIEW 2752 drw 02 The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGES ©1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391. 5.36 DECEMBER 1996 DSC-2752/6 1 1 page IDT72132, IDT72142 CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9 AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 5ns 1.5V 1.5V See Figure A 2752 tbl 08 COMMERCIAL TEMPERATURE RANGES 5V D.U.T. 680Ω 1.1K Ω 30pF* FUNCTIONAL DESCRIPTION 2752 drw 03 or equivalent circuit Figure A. Output Load *Includies jig and scope capacitances Serial Data Input The serial data is input on the SI pin. The data is clocked in on the rising edge of SICP providing the Full Flag (FF) is not asserted. If the Full Flag is asserted then the next parallel data word is inhibited from moving into the RAM array. NOTE: SICP should not be clocked once the last bit of the last word has been shifted in, as indicated by NW HIGH and FF LOW. If it is, then the input data will be lost. The serial word is shifted in Least Significant Bit first. Thus, when the FIFO is read, the Least Significant Bit will come out on Q0 and the second bit is on Q1 and so on. The serial word width must be programmed by connecting the appropriate Data Set line (D7, D8) to the NW input. The data set lines are taps off a digital delay line. Selecting one of these taps programs the width of the serial word to be written in. Parallel Data Output A read cycle is initiated on the falling edge of Read (R) provided the Empty Flag is not set. The output data is accessed on a first-in/first-out basis, independent of the ongoing write operations. The data is available tA after the falling edge of R and the output bus Q goes into high imped- ance after R goes HIGH. Alternately, the user can access the FIFO by keeping R LOW and enabling data on the bus by asserting Output Enable (OE). When R is LOW, the OE signal enables data on the output bus. When R is LOW and OE is HIGH, the output bus is three-stated. When R is HIGH, the output bus is disabled irrespective of OE. RS SICP R AEF, EF HF, FF D7 ,D8 t RSDL t RSC t RS t RSS tRSS tRSF1 tRSF2 tRSR 0 n-1 (1) t PDI NOTE: 1. Input bits are numbered 0 to n-1. D7 and D8 correspond to n=8 and n=9 respectively Figure 1. Reset 2752 drw 04 5.36 5 5 Page IDT72132, IDT72142 CMOS SERIAL-TO-PARALLEL FIFO 2048 x 9 AND 4096 x 9 COMMERCIAL TEMPERATURE RANGES Width Expansion Configuration In the cascaded case, word widths of more than 9 bits can be achieved by using more than one device. By tying the SIX line of the least significant device HIGH and the SIX of the subsequent devices to the appropriate Data Set lines of the previous devices, a cascaded serial word is achieved. On the first LOW-to-HIGH clock edge of SICP, both the Data Set lines go LOW. Just as in the standalone case, on each corresponding clock cycle, the equivalent Data Set line goes HIGH in order of least to most significant. SERIAL-IN CLOCK VCC SERIAL DATA IN XI SI Q 0-7 SICP FIFO #1 SIX NW D7 8 8 XI SI SICP FIFO #2 Q 0-7 PARALLEL DATA OUT 8 SIX NW D7 SOCP 0 D 7 OF FIFO #1 AND SIX OF FIFO #2 D 7 OF FIFO #2 AND NW TO FIFO #1 AND FIFO #2 1 7 8 9 10 14 15 Figure 14. Serial-In to Parallel-Out Data of 16 Bits 0 2752 drw 17 5.36 11 11 Page

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