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PDF IDT72131L35P Data sheet ( Hoja de datos )

Número de pieza IDT72131L35P
Descripción CMOS PARALLEL-TO-SERIAL FIFO 2048 X 9 4096 X 9
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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Integrated Device Technology, Inc.
CMOS PARALLEL-TO-SERIAL FIFO
2048 X 9
4096 X 9
IDT72131
IDT72141
FEATURES:
• 35ns parallel port access time, 45ns cycle time
• 50MHz serial port shift rate
• Expandable in depth and width with no external
components
• Programmable word lengths including 7-9, 16-18, 32-36
bit using Flexishiftserial output without using any
additional components
• Multiple status flags: Full, Almost-Full (1/8 from full),
Half-Full, Almost Empty (1/8 from empty), and Empty
• Asynchronous and simultaneous read and write
operations
• Dual-Port zero fall-through architecture
• Retransmit capability in single device mode
• Produced with high-performance, low power CMOS
technology
• Available in 28-pin plastic DIP
• Industrial temperature range (-40oC to +85oC) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT72131/72141 are high-speed, low power parallel-
to-serial FIFOs. These FIFOs are ideally suited to serial
communications applications, tape/disk controllers, and local
area networks (LANs). The IDT72131/72141 can be config-
ured with the IDTs serial-to-parallel FIFOs (IDT72132/72142)
for bidirectional serial data buffering.
The FIFO has a 9-bit parallel input port and a serial output
port. Wider and deeper parallel-to-serial data buffers can be
built using multiple IDT72131/72141 chips. IDTs unique
Flexishift serial expansion logic (SOX, NR) makes width
expansion possible with no additional components. These
FIFOs will expand to a variety of word widths including 8, 9, 16,
and 32 bits. The IDT72131/141 can also be directly connected
for depth expansion.
Five flags are provided to monitor the FIFO. The full and
empty flags prevent any FIFO data overflow or underflow
conditions. The almost-full (7/8), half-full, and almost empty
(1/8) flags signal memory utilization within the FIFO.
The IDT72131/72141 is fabricated using IDTs high-speed
submicron CMOS technology.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
W
WRITE
POINTER
D0-D 8
RAM ARRAY
2048 x 9
4096 x 9
FLAG
LOGIC
NEXT READ
POINTER
EF
AEF
/HF
FF
NR
RS
FL/RT
RESET LOGIC
XI
EXPANSION
LOGIC
XO/
SOCP
SERIAL OUTPUT
CIRCUITRY
SOX
SO
Q4 Q6 Q7 Q8
2751 drw 01
W
D4
D3
D2
D1
D0
XI
SOX
SOCP
SO
AEF
FF
Q4
GND
1 28 Vcc
2 27 D5
3 26 D6
4 25 D7
5 24 D8
6
P28-1
23
FL/RT
7
&
C28-3
22
RS
8 21 EF
9 20 XO/HF
10 19 GND
11 18 Q8
12 17 Q7
13 16 Q6
14 15 NR
DIP
TOP VIEW
2751 drw 02a
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
5.34
DECEMBER 1996
DSC-2751/6
1

1 page




IDT72131L35P pdf
IDT72131, IDT72141
CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
See Figure A
2751 tbl 08
COMMERCIAL TEMPERATURE RANGES
5V
D.U.T.
680
1.1K
30pF*
2751 drw 03
or equivalent circuit
Figure A. Ouput Load
*Including jig and scope capacitances
FUNCTIONAL DESCRIPTION
Parallel Data Input
The data is written into the FIFO in parallel through the
D0-8 input data lines. A write cycle is initiated on the falling
edge of the Write (W) signal provided the Full Flag (FF) is not
asserted. If the W signal changes from HIGH-to-LOW and the
Full-Flag (FF) is already set, the write line is inhibited internally
from incrementing the write pointer and no write operation
occurs.
Data set-up and hold times must be met with respect to the
rising edge of Write. The data is written to the RAM at the write
pointer. On the rising edge of W, the write pointer is
incremented. Write operations can occur simultaneously or
asynchronously with read operations.
Serial Data Output
The serial data is output on the SO pin. The data is clocked
out on the rising edge of SOCP providing the Empty Flag (EF)
is not asserted. If the Empty Flag is asserted then the next data
word is inhibited from moving to the output register and being
clocked out by SOCP. NOTE: SOCP should not be clocked
once the last bit of the last word has been clocked out. If it is,
then two things will occur. One, the SO pin will go High-Z and
two, SOCP will be out of sync with Next Read (NR).
The serial word is shifted out Least Significant Bit first, that
is the first bit will be D0, then D1 and so on up to the serial word
width. The serial word width must be programmed by connect-
ing the appropriate Data Set line (Q4, Q6, Q7 or Q8) to the NR
input. The Data Set lines are taps off a digital delay line.
Selecting one of these taps, programs the width of the serial
word to be read and shifted out.
RS
W
AEF, EF
HF, FF
SOCP
Q4, Q6, Q7, Q8
tRSQL
tRSC
tRS
tRSS
tRSF1
tRSF2
tRSS
Figure 1. Reset
tRSR
tRSR
tRSQH
2751 drw 04
5.34 5

5 Page





IDT72131L35P arduino
IDT72131, IDT72141
CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9
COMMERCIAL TEMPERATURE RANGES
Width Expansion Configuration
In the cascaded case, word widths of more than 9 bits can
be achieved by using more than one device. By tying the SOX
line of the least significant device HIGH and the SOX of the
subsequent devices to the appropriate Data Set lines of the
previous devices, a cascaded serial word is achieved.
On the first LOW-to-HIGH clock edge of SOCP, all lines go
LOW. Just as in the standalone case, on each corresponding
clock cycle, the equivalent Data Set line goes HIGH in order
of least to most significant. When the Data Set line which is
connected to the SOX input of the next device goes HIGH, the
D0 of that device goes HIGH, the cascading from one device
to the next. The Data Set line of the most significant bit
programs the serial word width by being connected to all NR
inputs.
The Serial Data Output (SO) of each device in the serial
word must be tied together. Since the SO pin is three stated,
only the device which is currently shifting out is enabled and
driving the 1-bit-bus.
SERIAL OUTPUT CLOCK
V CC
9 GND
D 0-8
SO
SOCP
SOX
NR
XI
FIFO #1
Q8
PARALLEL DATA IN
16-BITS WIDE
SERIAL DATA
OUTPUT
7
D 0-6
SO
SOCP
SOX
NR
GND
XI
FIFO #2
Q6
0 1 7 8 9 10 14 15 0
SOCP
Q 8 OF FIFO #1 AND
SOX OF FIFO #2
Q6 OF FIFO #2 AND
NR OF FIFO #1 AND
FIFO #2
2751 drw 16
Figure 13. Width Wxpansion for 16-bit Parallel Data In. The Parallel Data In is tied to D0-8 of FIFO #1 and D0-6 of FIFO #2.
5.34 11

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