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PDF IDT72125 Data sheet ( Hoja de datos )
| Número de pieza | IDT72125 | |
| Descripción | CMOS PARALLEL-TO-SERIAL FIFO | |
| Fabricantes | Integrated Device Technology | |
| Logotipo |  |
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CMOS PARALLEL-TO-SERIAL FIFO
1,024 x 16
IDT72125
FEATURES:
• 25ns parallel port access time, 35ns cycle time
• 50MHz serial shift frequency
• Wide x16 organization offering easy expansion
• Low power consumption (50mA typical)
• Least/Most Significant Bit first read selected by asserting the
FL/DIR pin
• Four memory status flags: Empty, Full, Half-Full, and Almost-
Empty/Almost-Full
• Dual-Port zero fall-through architecture
• Available in 28-pin 300 mil plastic DIP and 28-pin SOIC
• Green parts available, see ordering information
DESCRIPTION:
The IDT72125 is a high-speed, low- power, dedicated, parallel-to-serial
FIFO. This FIFO features a 16-bit parallel input port and a serial output port with
1,024 word depths, respectively.
The ability to buffer wide word widths (x16) make these FIFOs ideal for laser
printers, FAX machines, local area networks (LANs), video storage and disk/
tape controller applications.
Expansion in width and depth can be achieved using multiple chips. IDT’s
unique serial expansion logic makes this possible using a minimum of pins.
The unique serial output port is driven by one data pin (SO) and one clock
pin (SOCP). The Least Significant or Most Significant Bit can be read first by
programming the DIR pin after a reset.
Monitoring the FIFO is eased by the availability of four status flags: Empty,
Full,Half-FullandAlmost-Empty/Almost-Full. TheFullandEmptyflagsprevent
anyFIFOdataoverfloworunderflowconditions. TheHalf-FullFlagisavailable
in both single and expansion mode configurations. The Almost-Empty/Almost-
Full Flag is available only in a single device mode.
The IDT72125 is fabricated using submicron CMOS technology.
FUNCTIONAL BLOCK DIAGRAM
RS W
D0-15
16
RESET
LOGIC
WRITE
POINTER
RAM
ARRAY
1,024 x 16
READ
POINTER
RSIX
RSOX
FL/DIR
EXPANSION
LOGIC
SERIAL OUTPUT
LOGIC
SOCP
SO
FLAG
LOGIC
FF
EF
HF
AEF
2665 drw01
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
© 2016 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
FEBRUARY 2016
DSC-2665/1
1 page  
IDT72125 PARALLEL-TO-SERIAL CMOS FIFO
1,024 x 16
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/FallTimes
Input Timing Reference Levels
Output Reference Levels
OutputLoad
GND to 3.0V
5ns
1.5V
1.5V
See Figure A
CAPACITANCE (TA = +25°C, f = 1.0 MHz)
Symbol
Parameter(1)
Condition
CIN
COUT
Input Capacitance
Output Capacitance
VIN = 0V
VOUT = 0V
NOTE:
1. Characterized values, not currently tested.
Max.
10
12
Unit
pF
pF
COMMERCIAL TEMPERATURE RANGE
TO
OUTPUT
PIN
680Ω
5V
1.1KΩ
30pF *
2665 drw 03
or equivalent circuit
Figure A. Output Load
* Includes scope and jig capacitances.
FUNCTIONAL DESCRIPTION
PARALLEL DATA INPUT
The device must be reset before beginning operation so that all flags are
set to their initial state. In width or depth expansion the First Load pin (FL) must
be programmed to indicate the first device.
The data is written into the FIFO in parallel through the D0–D15 input data
lines. AwritecycleisinitiatedonthefallingedgeoftheWrite(W)signalprovided
the Full Flag (FF) is not asserted. If the W signal changes from HIGH-to-LOW
and the Full Flag (FF) is already set, the write line is internally inhibited internally
from incrementing the write pointer and no write operation occurs.
Dataset-upandholdtimesmustbemetwithrespecttotherisingedgeofWrite.
OntherisingedgeofW,thewritepointerisincremented. Writeoperationscan
occur simultaneously or asynchronously with read operations.
SERIAL DATA OUTPUT
The serial data is output on the SO pin. The data is clocked out on the rising
edge of SOCP providing the Empty Flag (EF) is not asserted. If the Empty Flag
is asserted then the next data word is inhibited from moving to the output register
and being clocked out by SOCP.
The serial word is shifted out Least Significant Bit or Most Significant Bit first,
depending on the FL/DIR level during operation. A LOW on DIR will cause the
Least Significant Bit to be read out first. A HIGH on DIR will cause the Most
Significant Bit to be read out first.
tRSC
tRS
RS
tRSS
W
tRSC
AEF , EF
HF , FF
tRSC
SOCP
tRSS
NOTE 2
tFLS
FL/DIR
NOTES:
1. EF, FF, HF and AEF may change status during Reset, but flags will be valid at tRSC.
2. SOCP should be in the steady LOW or HIGH during tRSS. The first LOW-HIGH (or HIGH-LOW) transition can begin after tRSR.
Figure 1. Reset
5
tRSR
FLAG
STABLE
tRSR
FLAG
STABLE
tFLH
2665 drw 04
5 Page 
ORDERING INFORMATION
XXXXX
X
XX
X
DeviceType Power Speed Package
XX X
Process/
Temperature
Range
BLANK
8
BLANK
Tube or Tray
Tape and Reel
Commercial (0OC to +70OC)
G Green
TP Plastic Thin DIP (300mil, P28)
SO Small Outline IC (Gull Wing, SOIC, SO28)
25
(50 MHz serial shift rate) Parallel Access Time
(tA) in Nanoseconds
L Low Power
72125
1,024 x 16-Bit Parallel-to-Serial FIFO
2665 drw17
DATASHEET DOCUMENT HISTORY
02/10/2016
pgs. 1-11
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
11
for Tech Support:
408-360-1753
email: [email protected]
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet IDT72125.PDF ] | |
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