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PDF IDT72105L50TP Data sheet ( Hoja de datos )

Número de pieza IDT72105L50TP
Descripción CMOS PARALLEL-TO-SERIAL FIFO 256 x 16/ 512 x 16/ 1024 x 16
Fabricantes Integrated Device Technology 
Logotipo Integrated Device Technology Logotipo



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Integrated Device Technology, Inc.
CMOS PARALLEL-TO-SERIAL FIFO
256 x 16, 512 x 16, 1024 x 16
IDT72105
IDT72115
IDT72125
FEATURES:
• 25ns parallel port access time, 35ns cycle time
• 45MHz serial output shift rate
• Wide x16 organization offering easy expansion
• Low power consumption (50mA typical)
• Least/Most Significant Bit first read selected by asserting
the FL/DIR pin
• Four memory status flags: Empty, Full, Half-Full, and
Almost-Empty/Almost-Full
• Dual-Port zero fall-through architecture
• Available in 28-pin 300 mil plastic DIP and 28-pin SOIC
• Industrial temperature range (-40oC to +85oC) is avail-
able, tested to military electrical specifications
DESCRIPTION:
The IDT72105/72115/72125s are very high-speed, low-
power,dedicated, parallel-to-serial FIFOs. These FIFOs
possess a 16-bit parallel input port and a serial output port with
256, 512 and 1K word depths, respectively.
The ability to buffer wide word widths (x16) make these
FIFOs ideal for laser printers, FAX machines, local area
networks (LANs), video storage and disk/tape controller
applications.
Expansion in width and depth can be achieved using
multiple chips. IDT’s unique serial expansion logic makes this
possible using a minimum of pins.
The unique serial output port is driven by one data pin (SO)
and one clock pin (SOCP). The Least Significant or Most
Significant Bit can be read first by programming the DIR pin
after a reset.
Monitoring the FIFO is eased by the availability of four
status flags: Empty, Full, Half-Full and Almost-Empty/Almost-
Full. The Full and Empty flags prevent any FIFO data overflow
or underflow conditions. The Half-Full Flag is available in both
single and expansion mode configurations. The Almost-Empty/
Almost-Full Flag is available only in a single device mode.
The IDT72105/15/25 are fabricated using IDT’s leading
edge, submicron CMOS technology. Military grade product is
manufactured in compliance with the latest revision of Mil-
STD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
RS W
D0–15
16
RESET
LOGIC
WRITE
POINTER
RAM
ARRAY
256 x 16
512 x 16
1024 x 16
READ
POINTER
RSIX
RSOX
FL/DIR
EXPANSION
LOGIC
SERIAL OUTPUT
LOGIC
FLAG
LOGIC
FF
EF
HF
AEF
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor Co.
SOCP
SO
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
5.35
2665 drw 01
DECEMBER 1996
DSC-2665/6
1

1 page




IDT72105L50TP pdf
IDT72105, IDT72115, IDT72125,
256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
See Figure A
2665 tbl 07
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions Max. Unit
CIN
Input Capacitance
VIN = 0V
10 pF
COUT
Output
Capacitance
VOUT = 0V
12 pF
NOTE:
1. This parameter is sampled and not 100% tested.
2665 tbl 08
COMMERCIAL TEMPERATURE RANGE
TO
OUTPUT
PIN
680
5V
1.1K
30pF*
2665 drw 03
or equivalent circuit
Figure A. Output Load
*Includes jig and scope capacitances.
FUNCTIONAL DESCRIPTION
Parallel Data Input
The device must be reset before beginning operation so
that all flags are set to their initial state. In width or depth
expansion the First Load pin (FL) must be programmed to
indicate the first device.
The data is written into the FIFO in parallel through the D0–
15 input data lines. A write cycle is initiated on the falling edge
of the Write (W) signal provided the Full Flag (FF) is not
asserted. If the W signal changes from HIGH-to-LOW and the
Full Flag (FF) is already set, the write line is internally inhibited
internally from incrementing the write pointer and no write
operation occurs.
Data set-up and hold times must be met with respect to the
rising edge of Write. On the rising edge of W, the write pointer
is incremented. Write operations can occur simultaneously or
asynchronously with read operations.
Serial Data Output
The serial data is output on the SO pin. The data is clocked
out on the rising edge of SOCP providing the Empty Flag (EF)
is not asserted. If the Empty Flag is asserted then the next data
word is inhibited from moving to the output register and being
clocked out by SOCP.
The serial word is shifted out Least Significant Bit or Most
Significant Bit first, depending on the FL/DIR level during
operation. A LOW on DIR will cause the Least Significant Bit
to be read out first. A HIGH on DIR will cause the Most
Significant Bit to be read out first.
RS
W
AEF, EF
HF, FF
SOCP
FL/DIR
tRSC
tRS
tRSS
tRSC
tRSC
tRSS
NOTE 2
tFLS
tRSR
tRSR
tFLH
NOTES:
1. EF, FF, HF and AEF may change status during Reset, but flags will be valid at tRSC.
2. SOCP should be in the steady LOW or HIGH during tRSS. The first LOW-HIGH (or HIGH-LOW) transition can begin after tRSR.
Figure 1. Reset
FLAG
STABLE
FLAG
STABLE
2665 drw 04
5.35 5

5 Page





IDT72105L50TP arduino
IDT72105, IDT72115, IDT72125,
256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO
PARALLEL DATAIN
ADDRESS
DECODER
74FCT138
00 01 10
COMMERCIAL TEMPERATURE RANGE
SERIAL OUTPUT CLOCK
LOW ON RESET
HIGH ON RESET
SOCP
D 0–15
FL/DIR
FIFO #1
W
RSIX
RSOX
SO
EF
HF
FF
SOCP
D 16–31
FL/DIR
FIFO #2
W
RSIX
RSOX
SO
EF
HF
FF
EMPTY
FLAG
SOCP
FL/DIR
D 0–15
FIFO #3
W RSIX RSOX SO
EF
HF
FF
SOCP
FL/DIR
D 16–31
FIFO #4
W
RSIX RSOX SO
EF
HF
FF
HALF-FULL
FLAG
SOCP
D 0–15
FL/DIR
FIFO #5
W
RSIX
RSOX
SO
EF
HF
FF
SOCP
D 16–31
FL/DIR
FIFO #6
W
RSIX
RSOX
SO
EF
HF
FF
Figure 13. A 3K x 32 Parallel-to-Serial FIFO using the IDT72125
FULL
FLAG
SERIAL DATA OUT
2665 drw 16
5.35 11

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