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Número de pieza | IDT72104 | |
Descripción | CMOS PARALLEL-SERIAL FIFO 2048 x 9/ 4096 x 9 | |
Fabricantes | Integrated Device Technology | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de IDT72104 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
No Preview Available ! CMOS PARALLEL-SERIAL FIFO
2048 x 9, 4096 x 9
IDT72103
IDT72104
Integrated Device Technology, Inc.
FEATURES:
• 35ns parallel port access time, 45ns cycle time
• 50MHz serial input/output frequency
• Serial-to-parallel, parallel-to-serial, serial-to-serial, and
parallel-to-parallel operations
• Expandable in both depth and width with no external
components
• Flexishift™ — Sets programmable serial word width
from 4 bits to any width with no external components
• Multiple flags: Full, Almost-Full (Full-1/8),Full-Minus-
One, Empty, Almost-Empty (Empty + 1/8), Empty-Plus
One, and Half-Full
• Asynchronous and simultaneous read or write
operations
• Dual-Port, zero fall-through time architecture
• Retransmit capability in single-device mode
• Packaged in 44-pin PLCC
• Industrial temperature range (-40oC to +85oC) is avail-
able, tested to military electrical specifications
APPLICATIONS:
• High-speed data acquisition systems
• Local area network (LAN) buffer
• High-speed modem data buffer
• Remote telemetry data buffer
• FAX raster video data buffer
• Laser printer engine data buffer
• High-speed parallel bus-to-bus communications
• Magnetic media controllers
• Serial link buffer
DESCRIPTION:
The IDT72103/72104 are high-speed Parallel-Serial FlFOs
to be used with high-performance systems for functions such
as serial communications, laser printer engine control and
local area networks.
A serial input, a serial output and two 9-bit parallel ports
make four modes of data transfer possible: serial-to-parallel,
parallel-to-serial, serial-to-serial, and parallel-to-parallel. The
IDT72103/72104 are expandable in both depth and width for
all of these operational configurations.
FUNCTIONAL BLOCK DIAGRAM
SERIAL
INPUT
SI
SIX
SICP
SERIAL
INPUT
CIRCUITRY
SI/PI
SO/PO
SERIAL/
PARALLEL
CONTROL
W
XI
XO
FL/RT
WRITE
POINTER
DEPTH
EXPANSION
LOGIC
DATA INPUTS (D0-D 8 )
RAM ARRAY
2048 x 9
4096 x 9
FLAG
LOGIC
READ
POINTER
RESET
LOGIC
FF
FF-1
EF+1
EF
AEF
HF
R
RS
SERIAL
OUTPUT
SERIAL
SO
OE
OUTPUT
SOX
CIRCUITRY
SOCP
DATA OUTPUTS (Q0 -Q 8 )
2753 drw 01
The IDT logo is a registered trademark of Integrated Device Technology,Inc.
COMMERCIAL TEMPERATURE RANGES
©1996 Integrated Device Technology, Inc.
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
5.37
DECEMBER 1996
DSC-2753/8
1
1 page IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 x 9
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C)
IDT72103/72104
Commercial
tA = 35, 50ns
Symbol
Parameter
Min.
Typ.
Max.
I (1)
IL
Input Leakage Current
(Any Input)
–1 —
1
I (2)
OL
Output Leakage Current
–10 —
10
VOH Output Logic "1" Voltage,
IOUT = -2mA(4)
2.4 — —
VOL Output Logic "0" Voltage,
IOUT = 8mA(5)
— — 0.4
I (3)
CC1
Average VCC Power Supply Current
—
90 140
I (3)
CC2
Average Standby Current
(R = W = RS = FL/RT = VIH)
(SOCP = SICP = VIL)
— 8 12
ICC3(L)(3,6) Power Down Current
——
2
NOTES:
1.
2.
Measurements
R ≥ VIH, SOCP
with 0.4 ≤ VIN ≤ VCC.
≤ VIL, 0.4 ≤ VOUT ≤ VCC.
3. ICC measurements are made with outputs open.
4. For SO, IOUT = -8mA.
5. For SO, IOUT =16mA.
6. SOCP = SICP ≤ 0.2V; other Inputs = VCC -0.2V.
COMMERCIAL TEMPERATURE RANGES
Unit
µA
µA
V
V
mA
mA
mA
2753 tbl 06
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1
2753 tbl 07
D.U.T.
680Ω
5V
1.1KΩ
30pF*
2753 drw 04
or equivalent circuit
Figure 1. Ouput Load
*Including jig and scope capacitances
5.37 5
5 Page IDT72103, IDT72104
CMOS PARALLEL-SERIAL FIFO 2048 x 9 AND 4096 x 9
R
COMMERCIAL TEMPERATURE RANGES
(1)
EF
t REF(2)
(3)
W
t WEF
NOTES:
2753 drw 09
1. Data is valid on this edge.
2. The Empty Flag is asserted by R in the Parallel-Out mode and is specified by tREF. The EF flag is deasserted by the rising edge of W.
3. First rising edge of Write after EF is set.
Figure 6. Empty Flag Timings in Parallel Out Mode
W
FF
tRFF (1)
R
tWFF
NOTE:
2753 drw 10
1. For the assertion time, tWFF is used when data is written in the Parallel mode. The FF is de-asserted by the rising edge of R.
Figure 7. Full Flag Timings in Parallel-In Mode
t WF
W
R
Almost
AEF Empty
Figure 8. Almost-Empty Flag Region
W
t RF
R
Almost
Empty
2753 drw 11
AEF
t WF
t RF
Almost
Full
Figure 9. Almost-Full Flag Region
2753 drw 12
5.37 11
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet IDT72104.PDF ] |
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