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Número de pieza | UC3844D | |
Descripción | HIGH PERFORMANCE CURRENT MODE CONTROLLERS | |
Fabricantes | ON Semiconductor | |
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No Preview Available ! UC3844, UC3845, UC2844,
UC2845
High Performance
Current Mode Controllers
The UC3844, UC3845 series are high performance fixed frequency
current mode controllers. They are specifically designed for Off−Line
and DC−to−DC converter applications offering the designer a cost
effective solution with minimal external components. These integrated
circuits feature an oscillator, a temperature compensated reference, high
gain error amplifier, current sensing comparator, and a high current
totem pole output ideally suited for driving a power MOSFET.
Also included are protective features consisting of input and
reference undervoltage lockouts each with hysteresis, cycle−by−cycle
current limiting, a latch for single pulse metering, and a flip−flop which
blanks the output off every other oscillator cycle, allowing output dead
times to be programmed for 50% to 70%.
These devices are available in an 8−pin dual−in−line plastic package
as well as the 14−pin plastic surface mount (SOIC−14). The SOIC−14
package has separate power and ground pins for the totem pole output
stage.
The UCX844 has UVLO thresholds of 16 V (on) and 10 V (off),
ideally suited for off−line converters. The UCX845 is tailored for
lower voltage applications having UVLO thresholds of 8.5 V (on) and
7.6 V (off).
Features
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• Current Mode Operation to 500 kHz Output Switching Frequency
• Output Deadtime Adjustable from 50% to 70%
• Automatic Feed Forward Compensation
• Latching PWM for Cycle−By−Cycle Current Limiting
• Internally Trimmed Reference with Undervoltage Lockout
• High Current Totem Pole Output
• Input Undervoltage Lockout with Hysteresis
• Low Startup and Operating Current
• Direct Interface with ON Semiconductor SENSEFETt Products
• Pb−Free Packages are Available
VCC 7(12)
Vref
8(14)
RTCT
4(7)
Voltage
Feedback
2(3)
1(1)
Output
Comp.
R
5.0V
Reference
VCC
Undervoltage
Lockout
R
Vref
Undervoltage
Lockout
Oscillator
+
−
Error
Amplifier
Flip
Flop
&
Latching
PWM
GND 5(9)
Pin numbers in parenthesis are for the D suffix SOIC−14 package.
Figure 1. Simplified Block Diagram
VC
7(11)
Output
6(10)
PWR GND
5(8)
Current
Sense
3(5)
© Semiconductor Components Industries, LLC, 2006
July, 2006 − Rev. 7
1
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8
1
14
1
8
1
PDIP−8
N SUFFIX
CASE 626
SOIC−14
D SUFFIX
CASE 751A
SOIC−8
D1 SUFFIX
CASE 751A
PIN CONNECTIONS
Compensation 1
Voltage Feedback 2
Current Sense 3
RT/CT 4
8 Vref
7 VCC
6 Output
5 GND
(Top View)
Compensation 1
NC 2
Voltage Feedback 3
NC 4
Current Sense 5
NC 6
RT/CT 7
14 Vref
13 NC
12 VCC
11 VC
10 Output
9 GND
8 Power Ground
(Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page page 14 of this data sheet.
Publication Order Number:
UC3844/D
1 page UC3844, UC3845, UC2844, UC2845
0
−4.0
−8.0
−12
−16
−20
−24
0
VCC = 15 V
TA = 125°C
TA = −55°C
TA = 25°C
20 40 60 80 100
Iref, REFERENCE SOURCE CURRENT (mA)
Figure 8. Reference Voltage Change
versus Source Current
120
110
VCC = 15 V
RL ≤ 0.1 W
90
70
50
−55 −25
0
25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C)
Figure 9. Reference Short Circuit Current
versus Temperature
VCC = 15 V
IO = 1.0 mA to 20 mA
TA = 25°C
VCC = 12 V to 25 V
TA = 25°C
2.0 ms/DIV
Figure 10. Reference Load Regulation
2.0 ms/DIV
Figure 11. Reference Line Regulation
0
VCC
Source Saturation
(Load to Ground)
VCC = 15 V
80 ms Pulsed Load
−1.0 TA = 25°C
120 Hz Rate
−2.0
TA = −55°C
3.0
TA = −55°C
2.0
TA = 25°C
1.0
0
0
Sink Saturation
(Load to VCC)
GN
D
200 400 600
IO, OUTPUT LOAD CURRENT (mA)
800
Figure 12. Output Saturation Voltage
versus Load Current
90%
10%
VCC = 15 V
CL = 1.0 nF
TA = 25°C
50 ns/DIV
Figure 13. Output Waveform
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5
5 Page UC3844, UC3845, UC2844, UC2845
VCC
7(12)
Vin
5.0Vref
+ +−
−
+− +
−
T
S
−
+
Q
R
Comp/Latch
7(11)
Rg
6(10)
5(8)
3(5)
Q1
RS
Series gate resistor Rg will damp any high frequency parasitic oscillations
caused by the MOSFET input capacitance and any series wiring inductance
in the gate−source circuit.
Figure 25. MOSFET Parasitic Oscillations
IB Vin
+
0
Base
−
Charge
Removal
C1
Q1
6(1)
5(8)
3(5)
RS
The totem−pole output can furnish negative base current for enhanced
transistor turn−off, with the addition of capacitor C1.
Figure 26. Bipolar Transistor Drive
8(14) R
Bias
R
5.0Vref
+−
+ +−
−
T
S
−+ RQ
Comp/Latch
7(12)
+
−
VCC Vin
Isolation
Boundary
7(11)
6(10)
5(8)
R
Q1
ÉÉ É+
0
ÉÉ ÉÉ−
VGS Waveforms
+
0
−
50% DC
25% DC
Ipk =
V(pin 1) − 1.4
3 RS
NP
NS
3(5) C RS NS
Np
MCR 2N
101 3905
4(7)
2(3)
1(1)
2N
3903
OSC
+
+−
EA
1.0mA
2R
R
5(9)
The MCR101 SCR must be selected for a holding of less than 0.5 mA at TA(min).
The simple two transistor circuit can be used in place of the SCR as shown. All
resistors are 10 k.
Figure 27. Isolated MOSFET Drive
Figure 28. Latched Shutdown
From VO
Ri
Rd CI
Rf ≥ 8.8 k
2.5V +
2(3) +− 1.0mA
Rf
EA 2R
R
1(1)
5(9)
Error Amp compensation circuit for stabilizing any current−mode topology except
for boost and flyback converters operating with continuous inductor current.
From VO
Rp Ri
Cp Rd CI
2.5V +
2(3) + 1.0mA
Rf
−
EA
2R
R
1(1)
5(9)
Error Amp compensation circuit for stabilizing current−mode boost and flyback
topologies operating with continuous inductor current.
Figure 29. Error Amplifier Compensation
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11
11 Page |
Páginas | Total 16 Páginas | |
PDF Descargar | [ Datasheet UC3844D.PDF ] |
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