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PDF 74173 Data sheet ( Hoja de datos )
| Número de pieza | 74173 | |
| Descripción | 4-bit D-type Register (with 3-state Outputs) | |
| Fabricantes | Hitachi Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 74173 (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
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HD74HC173
4-bit D-type Register (with 3-state Outputs)
Description
The four D type Flip-Flops operate synchronously from a common clock. The 3-state outputs allow the
device to be used in bus organized systems. The outputs are placed in the 3-stage mode when either of the
output disable pins are in the logic high level.
The input disable allows the flip-flops to remain in their present states without having to disrupt the clock.
If either of the 2 input disables are taken to a logic high level, the Q outputs are fed back to the inputs,
forcing the flip-flops to remain in the same state. Clearing is enabled by taking the clear input to a logic
high level. The data outputs change state on the positive going edge of the clock.
Features
• High Speed Operation: tpd (Clock to Q) = 14 ns typ (CL = 50 pF)
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Function Table
Inputs
Data Enable
Clear
Clock
G1
G2
Data D
Output Q
HX X X X L
L L X X X Q0
L H X X Q0
L X H X Q0
L LL L L
L LL HH
Note: When either M or N (or both) is (are) high the output is disabled to the high-impedance state;
however sequential operation of the flip-flops is not affected.
1 page  
HD74HC173
AC Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Ta = 25°C
Ta = –40 to
+85°C
Item
Maximum clock
frequency
Symbol
f max
VCC (V)
2.0
4.5
Min Typ Max Min
——5 —
— — 27 —
Max Unit Test Conditions
4 MHz
21
6.0 — — 32 — 25
Propagation delay tPLH
time
t PHL
2.0 — — 175 — 220 ns Clock to Q
4.5 — 14 35 — 44
6.0 — — 30 — 37
tPHL 2.0 — — 150 — 190 ns Clear to Q
4.5 — 14 30 — 38
6.0 — — 26 — 33
Enable time tZH 2.0 — — 150 — 190 ns
tZL 4.5 — 12 30 — 38
6.0 — — 26 — 33
Disable time
t HZ
t LZ
2.0 — — 150 — 190 ns
4.5 — 12 30 — 38
6.0 — — 26 — 33
Setup time
tsu 2.0 100 — — 125 — ns
4.5 20 4 — 25 —
6.0 17 – — 21 —
Removal time
t rem
2.0 90 — — 115 — ns
4.5 18 0 — 23 —
6.0 15 — — 20 —
Hold time
th 2.0 5 — — 5 — ns
4.5 5 –2 — 5 —
6.0 5 — — 5 —
Pulse width tw 2.0 80 — — 100 — ns
4.5 16 4 — 20 —
6.0 14 — — 17 —
Output rise/fall
time
t TLH
t THL
2.0 — — 60 — 75 ns
4.5 — 4 12 — 15
6.0 — — 10 — 13
Input capacitance Cin — — 5 10 — 10 pF
5
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet 74173.PDF ] | |
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