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PDF 73M2910L Data sheet ( Hoja de datos )

Número de pieza 73M2910L
Descripción Microcontroller
Fabricantes ETC 
Logotipo ETC Logotipo



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DESCRIPTION
The 73M2910L high performance micro-controller is
based on the industry standard 8-bit 8032
implemented in an advanced submicron CMOS
process. The processor has the attributes of the
8032, including instruction cycle time, UART, timers,
interrupts, 256 bytes of on-chip RAM and
programmable I/O. The architecture has been
optimized for low power portable modem or
communication applications by integrating unique
features with the core CPU.
A key feature is a user friendly HDLC Packetizer,
accessed through the special function registers. It
has a serial I/O, hardware support for 16 and 32-bit
CRC, zero insert/delete control, a dedicated interrupt
and a clear channel mode for by-passing the
packetizer.
Other features include additional user programmable
I/O with programmable bank select and chip select
logic, designed to eliminate board level glue logic. It
also includes two general-purpose input ports with
programmable wakeup capability.
For devices that require non-multiplexed address
and data buses, eight latched outputs for the low
byte of the address are available.
(continued)
BLOCK DIAGRAM
73M2910L
Microcontroller
April 2000
FEATURES
8032 compatible instruction set
44 MHz Operation from 3.3 to 5.5V
HDLC support logic (Packetizer, 16 and 32
CRC, zero ID)
24 pins for user programmable I/O ports
8 pins programmable chip select logic or I/O
for memory mapped peripheral eliminating
glue logic
3 external interrupt sources (programmable
polarity)
16 dedicated latched address pins
Multiplexed data/address bus
Instruction cycle time identical to 8032
Buffered oscillator (or OSC/2) output pin
1.8432 MHz UART clock available
Bank select circuitry to support up to 128k of
external program memory
Also available in 100-Lead QFP and 100-Pin
PGA packages
(2:0)
INTERRUPT
CONTROL
USR 1.0
USR 1.1
USR 1.2
USR 1.3
TIMERS
RXD
TXD
PTXCLK
PTXD
PRXCLK
PRXD
UART
HDLC
TIME GEN
CPU
SFR BUS
RAM 256 X 8
ALE
MEM I/O CTRL
A (15:0)
D (7:0)
USR I/O
USR5 (1:0)
CSB (7:0)
USR3 (7:0)
USR I/O
USR2 (7:0)
USR1 (7:0)

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73M2910L pdf
73M2910L
Microcontroller
BIT 4 Clock 2 Output Enable
Bit 4 enables the clock at the CLOCK 2 output pin if it is set to a 1. The CLOCK 2 pin output is held to a 0, by
writing this bit to a 0. This will reduce system power if the clock pin is not used or if a power reduction mode is
required.
BITS 3,2 Clock 2 Output Control
These bits determine the oscillator divisor for the CLOCK 2 output pin. They were designed to provide a
1.8432 MHz clock for an external UART given an oscillator frequency of 11.0592 MHz, 22.1184 MHz,
18.432 MHz, or 13.824 MHz.
BIT 3
0
0
1
1
BIT 2
0
1
0
1
CLK 2 OUT
OSC/7.5
OSC/6
OSC/12
OSC/10
OSC FREQUENCY
13.824 MHz
11.059 MHz
22.118 MHz
18.432 MHz
BIT 1 Clock 1 Output Enable
Bit 1 enables the clock at the clock 1 output pin if it is set to a 1. The clock pin output is held to a 0, by writing a
0 to this bit. This will reduce system power if the clock pin is not used or if a power reduction mode is required.
Bit 6 is cleared to a 0 upon a reset.
BIT 0 Clock 1 Output Control
Bit 0 controls the frequency of the clock 1 output pin. The clock output is either the oscillator’s output signal
divided by two or a buffered oscillator output signal.
POWER SAVING MODES
Low Power Modes
The 73M2910L supports two power conservation modes, which are controlled by the PCON.1 and PCON.0
control bits of the PCON Register.
If PCON.0 is set, the 73M2910L will go into a power saving mode where the oscillator is running, clocks are
supplied to the UART, timers, HDLC, and interrupt blocks, but no clocks are supplied to the CPU. Instruction
processing and activity on the address and data ports is halted. Normal operation is resumed when an
unmasked interrupt is requested or when a reset occurs.
If PCON.1 is set, the 73M2910L goes into its lowest power mode where the oscillator is halted. The total current
consumption in this state should be less than 10 µa. The 73M2910L will start its oscillator and begin to return to
normal operation when either a reset occurs, when a falling (rising if corresponding direction bit is set) edge of
an unmasked external interrupt from pins INT(2:0) is detected, or when the USR5 (1:0) pins change to a state
according to the USR5 port register. Edges used in wakeup modes are not filtered in the
73M2910L, so the user must be cautious of noise or small glitches inadvertently waking up the chip. From the
time the edge that results in the wake up occurs, to the point at which an instruction is executed, depends on
the oscillator start-up time. Three good oscillator pulses must be detected before the main internal clocks are
generated.
During power-down mode, both the ALE and PSEN pins are pulled high since these signals often provide the
output enable and chip enable for the ROM (active low). This ensures that the external components are in their
lowest power state.
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73M2910L arduino
73M2910L
Microcontroller
The chip selects partition a 64K memory space as follows:
CHIP SELECT PIN
RESERVED FOR INTERNAL USE
CS0 (USR4.0)
CS1 (USR4.1)
CS2 (USR4.2)
CS3 (USR4.3)
CS4 (USR4.4)
CS5 (USR4.5)
CS6 (USR4.6)
CS7 (USR4.7)
ADDRESS
0000H - 00FFH
0100H - 01FFH
0200H - 03FFH
0400H - 07FFH
0800H - 0FFFH
1000H - 1FFFH
2000H - 3FFFH
4000H - 7FFFH
8000H - FFFFH
# BYTES
256
256
512
1K
2K
4K
8K
16K
32K
NOTE:External addresses 0000H-00FFH may not be read. These are reserved for 73M2910L internally defined
registers
USR5 PORT
USR5 Port Register External Address 0006h
Byte Addressable
Reset State 60h
BIT 7
USR5EN
BIT 6
USR5.0
BIT 5
USR5.1
BIT 4
POL5.0
BIT 3
POL5.1
BIT 2
ACTE0
BIT 1
ACTE1
BIT 0
AND01
This register allows user programmable wakeup capability. If this is not required, this register can be used to
read external signals at the USR5.1 and USR5.0 pins.
Bit 7 USR5 Input Port Enable
Bit 7 is used to enable the USR5.1 and USR5.0 input circuitry. If this bit is a 0, the USR5 pin output circuitry is
driven to a known level internally and any signal level at the pin is ignored. When set to a 1 the pin input
circuitry is enabled and the values of these pins are reflected in bits 6 and 7. If these pins are not connected at
the board level, this bit should remain at a 0 to keep the pin input circuitry from drawing unnecessary current.
The USR5 Register can be programmed such that a transition (bit 4 determines rising or falling) of USR5.0, a
transition (bit 3 determines rising or falling) of USR5.1, or the logical combination of USR5.0 (bit 4 determines
high or low level) AND USR5.1 (bit 3 determines high or low level) can wakeup the processor from its
power-down mode.
BIT 6 USR5.0
Bit 6 reflects the value of chip pin USR5.0 if the USR5EN bit is set to a 1.
BIT 5 USR5.1
Bit 5 reflects the value of chip pin USR5.1 if the USR5EN bit is set to a 1.
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