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PDF 73K224BL Data sheet ( Hoja de datos )

Número de pieza 73K224BL
Descripción Single-Chip Modem w/ Integrated Hybrid
Fabricantes ETC 
Logotipo ETC Logotipo



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73K224BL
V.22bis/V.22/V.21/Bell 212A/103
Single-Chip Modem w/ Integrated Hybrid
DESCRIPTION
The 73K224BL is a highly integrated single-chip
modem IC which provides the functions needed to
construct a V.22bis compatible modem, capable of
2400 bit/s full-duplex operation over dial-up lines.
The 73K224BL is an enhancement of the 73K224L
single-chip modem which adds the hybrid hook
switch control, and driver to the 73K224L. The
73K224BL integrates analog, digital, and switched-
capacitor array functions on a single chip, offering
excellent performance and a high level of functional
integration in a 32-Lead PLCC and 44-Lead TQFP
package.
The 73K224BL operates from a single +5 V supply
for low power consumption.
The 73K224BL is designed to appear to the systems
designer as a microprocessor peripheral, and will
easily interface with popular single-chip micro-
processors (80C51 typical) for control of modem
functions through its 8-bit multiplexed address/data
bus or via an optional serial control bus. An ALE
control simplifies address demultiplexing. Data
communications normally occur through a separate
serial port.
(continued)
FEATURES
April 2000
Includes features of 73K224L single-chip
modem
On chip 2-wire/4-wire hybrid driver and off
hook relay buffer driver
One-chip multi-mode V.22bis/V.22/V.21 and
Bell 212A/103 compatible modem data pump
FSK (300 bit/s), DPSK (600, 1200 bit/s), or
QAM (2400 bit/s) encoding
Software compatible with other TDK
Semiconductor K-Series one-chip modems
Interfaces directly with standard micro-
processors (80C51 typical)
Parallel or serial bus for control
Selectable internal buffer/debuffer and
scrambler/descrambler functions
All asynchronous and synchronous
operating modes (internal, external, slave)
(continued)
BLOCK DIAGRAM
OH
8-BIT
µP
BUS
INTERFACE
TXD
RXD
SERIAL
INTERFACE
FSK
MODULATOR
DTMF,
ANSWER,
GUARD &
CALLING
TONE
GENERATOR
BUFFER
SCRAMBLER
DI-BIT/
QUAD-BIT
ENCODER
FIR
PULSE
SHAPER
QAM/
DPSK
MODULATOR
EQUALIZER
FILTER
FILTER
ATTENUATOR
DEBUFFER
DESCRAMBLER
DI-BIT/
QUAD-BIT
DECODER
DIGITAL
SIGNAL
PROCESSOR
RECEIVE
FUNCTIONS
TONE
DETECTION
FILTER
A/D
EQUALIZER
FIXED
DEMODULATOR
FILTER
AGC
2W/4W
HYBRID
GAIN
BOOST
FILTER
TXA1
TXA2
RXA

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73K224BL pdf
PIN DESCRIPTION
POWER
NAME
GND
VDD
PIN
1
16
VREF
31
ISET
28
73K224BL
V.22bis/V.22/V.21/Bell 212A/103
Single-Chip Modem w/ Integrated Hybrid
TYPE
I
I
O
I
DESCRIPTION
System ground
Power supply input, 5 V ±10% (73K224BL). Bypass with 0.1
and 22 µF capacitors to GND.
An internally generated reference voltage. Bypass with
0.1 µF capacitor to ground.
Chip current reference. Sets bias current for op-amps. The
chip current is set by connecting this pin to VDD through a
2 Mresistor. ISET should be bypassed to GND with a
0.1 µF capacitor.
PARALLEL MICROPROCESSOR CONTROL INTERFACE MODE
ALE
AD0-AD7
CS
CLK
INT
RD
RESET
13
5-12
23
2
20
15
30
I ADDRESS LATCH ENABLE: The falling edge of ALE latches
the address on AD0-AD2 and the chip select on CS.
I/O ADDRESS/DATA BUS: These bi-directional tri-state
multiplexed lines carry information to and from the internal
registers.
I CHIP SELECT: A low on this pin during the falling edge of
ALE allows a read cycle or a write cycle to occur. AD0-AD7
will not be driven and no registers will be written if CS
(latched) is not active. The state of CS is latched on the
falling edge of ALE.
O OUTPUT CLOCK: This pin is selectable under processor
control to be either the crystal frequency (for use as a
processor clock) or 16 times the data rate for use as a baud
rate clock in DPSK modes only. The pin defaults to the
crystal frequency on reset.
O INTERRUPT: This open drain output signal is used to inform
the processor that a detect flag has occurred. The processor
must then read the Detect Register to determine which detect
triggered the interrupt. INT will stay low until the processor
reads the detect register or does a full reset.
I READ: A low requests a read of the 73K224BL internal
registers. Data can not be output unless both RD and the
latched CS are active or low.
I RESET: An active high signal on this pin will put the chip into
an inactive state. All Control Register bits (CR0, CR1, tone)
will be reset. The output of the CLK pin will be set to the
crystal frequency. An internal pull-down resistor permits
power-on-reset using a capacitor to VDD.
5

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73K224BL arduino
73K224BL
V.22bis/V.22/V.21/Bell 212A/103
Single-Chip Modem w/ Integrated Hybrid
CONTROL REGISTER 0 (continued)
CR0
D7
D6
D5
D4
D3
D2
D1
D0
ADDR
000
BIT
D7
MODUL. MODUL.
OPTION TYPE 1
NAME
Modulation
Option
MODUL. TRANSMIT TRANSMIT TRANSMIT TRANSMIT ANSWER/
TYPE 0
MODE 2
MODE 1
MODE 0
ENABLE ORIGINATE
CONDITION DESCRIPTION
0 QAM selects 2400 bit/s. DPSK selects 1200 bit/s.
FSK selects 103 mode.
1 DPSK selects 600 bit/s.
FSK selects V.21 mode.
CONTROL REGISTER 1
CR1
D7
D6
D5
ADDR
001
TRANSMIT
PATTERN
1
TRANSMIT
PATTERN
0
ENABLE
DETECT
INTERRUPT
BIT
NAME
CONDITION
D0, D1
Test Mode
D1 D0
00
01
10
11
D2 Reset 0
1
D3 Clock Control 0
1
D4
BYPASS
SCRAMBLER
D3
CLOCK
CONTROL
D2
RESET
D1
TEST
MODE 1
D0
TEST
MODE 0
DESCRIPTION
Selects normal operating mode
Analog loopback mode. Loops the transmitted analog
signal back to the receiver, and causes the receiver to
use the same carrier frequency as the transmitter. To
squelch the TXA pin, transmit enable bit as well as Tone
Register bit D2 must be low.
Selects remote digital loopback. Received data is looped
back to transmit data internally, and RXD is forced to a
mark. Data on TXD is ignored.
Selects local digital loopback. Internally loops TXD back
to RXD and continues to transmit data carrier at TXA pin
Selects Normal Operations
Resets modem to power-down state. All Control
Register bits (CR0, CR1, CR2, CR3 and tone) are reset
to zero except CR3 bit D2. The output of the clock pin
will be set to the crystal frequency.
Selects 11.0592 MHz crystal echo output at CLK pin
Selects 16 times the data rate output at CLK pin in
DPSK/QAM modes only.
11

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