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PDF 73K222AU-IH Data sheet ( Hoja de datos )

Número de pieza 73K222AU-IH
Descripción Single-Chip Modem Modem with UART
Fabricantes ETC 
Logotipo ETC Logotipo



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DESCRIPTION
The 73K222AU is a compact, high-performance
modem which includes a 8250A/16C450 compatible
UART with the 1200 bit/s modem function on a
single chip. Based on the 73K222L 5V low power
CMOS modem IC, the 73K222AU is the perfect
modem/UART component for integral modem
applications. It is ideal for applications such as
portable terminals and laptop computers. The
73K222AU is the first fully featured modem IC which
can function as an intelligent modem in integral
applications without requiring a separate dedicated
microcontroller. It provides for data communication
at 1200, 600, and 300 bit/s in a multi-mode manner
that allows operation compatible with both Bell
212A/103 and CCITT V.22/V.21 standards. The
digital interface section contains a high speed
version of the industry standard 8250A/16C450
UART, commonly used in personal computer
products. A unique feature of the 73K222AU is that
the UART section can be used without the modem
function, providing an additional asynchronous port
at no added cost. The 73K222AU is designed in
CMOS technology and operates from a single +5V
supply. Available packaging includes 40-pin DIP or
44-pin PLCC for surface mount applications.
73K222AU
Single-Chip Modem
Modem with UART
FEATURES
April 2000
Modem/UART combination optimized for
integral bus applications
Includes features of 73K222L single-chip modem
Fully compatible 16C450/8250 UART with
8250B or 8250A selectable interrupt emulation
High speed UART will interface directly with
high clock rate bus with no wait states
Single-port mode allows full modem and
UART control from CPU bus, with no
dedicated microprocessor required
Dual-port mode suits conventional designs
using local microprocessor for transparent
modem operation
Complete modem functions for 1200 bit/s (Bell
212A, V.22) and 0-300 bit/s (Bell 103, V.21)
Includes DTMF generator, carrier, call-
progress and precise answer-tone detectors
for intelligent dialing capability
On chip 2-wire/4-wire hybrid driver and off-
hook relay buffer
Speaker output with four-level software driven
volume control
Low power CMOS (40 mW) with power down
mode (15 mW)
Operates from single +5V supply
BLOCK DIAGRAM
TXD
XTL1 XTL2 CLK
UD0
UD1
UD2
UD3
UD4
UD5
UD6
UD7
UA0
UA1
UA2
1.8432 MHz
8250A / 16C450
UART
INTERNAL DATA
73K222AL
2W/4W
HYBRID
2
INT OUT1
RXD-INPUT
OH
RELAY
DRIVER
TXA1
TXA2
RXA
SPKR
( ) / MA0
( ) / MA1
(UA3) / MA2
DATA / ( )
/( )
/ (N/C)
( ) / DCLK
( )/
INTRPT ( ) PRST RESET RXD
VDD VREF GND ISET STNDLN

1 page




73K222AU-IH pdf
73K222AU
Single-Chip Modem
with UART
UART INTERFACE
NAME
UA2-UA0
UA3
UDO-UD7
DISTR
DOSTR
CS@
INTRPT
RXD
DIP
37-39
12
27-34
35
36
1
5
6
PLCC
41-43
14
30-37
38
39
2
7
8
TYPE
I
I
I/O
I
I
I
O
I/O
DESCRIPTION
UART Address. These pins determine which of the UART
registers is being selected during a read or write on the UART
data bus. The contents of the DLAB bit in the UART’s Line
Control Register also control which register is referenced. In
single-port mode, UA0-UA3 are latched when ADS goes high.
In dual-port, only UA0-UA2 are used.
(3 state) UART Data. Data or control information to the UART
registers is carried over these lines.
Data Input Strobe. A low on this pin requests a read of the
internal UART registers. Data is output on the D0-D7 lines if
DISTR and CS@ are active.
Data Output Strobe. A low on this pin requests a write of the
internal UART registers. Data on the D0-D7 lines are latched on
the rising edge of DOSTR. Data is only written if both DOSTR
and CS@ are active.
Chip Select. A low on this pin allows a read or write to the
UART registers to occur. In single port mode, CS@ is latched
on ADS.
(3 state) UART Interrupt. This signal indicates that an interrupt
condition on the UART side has occurred. If the Enable 8250A
interrupt bit in the interrupt Enable Register is 0 the interrupt is
gated by the DISTR signal to provide compatibility with the
8250B. The output can be put in a high impedance state with
the OUT2 register bit in the Modem Control Register. In single-
port mode, INTRPT also becomes valid when a modem
interrupt signal is generated by the modem section’s Detect
Register.
Function is determined by STNDLN pin and bit 7, Tone Control
Register:
STNDLN D7
0 0 RXD outputs data received by modem.
1 0 RXD is electrically an input but signal is
ignored.
X 1 RXD is a serial input to UART.
5

5 Page





73K222AU-IH arduino
73K222AU
Single-Chip Modem
with UART
UART CONTROL REGISTER OVERVIEW
REGISTER
RECEIVER
BUFFER
REGISTER
(READ ONLY)
TRANSMIT
HOLDING
REGISTER
(WRITE ONLY)
RBR
THR
INTERRUPT
ENABLE
REGISTER
IER
INTERRUPT
ID
REGISTER
(READ ONLY)
IIR
LINE
CONTROL
REGISTER
LCR
UART
ADDRESS
UA3-UA0*
0000
DLAB = 0
0000
DLAB = 0
0001
DLAB = 0
0010
0011
MODEM
CONTROL
REGISTER
MCR
0100
LINE
STATUS
REGISTER
MODEM
STATUS
REGISTER
(READ ONLY)
LSR
MSR
0101
0110
SCRATCH
REGISTER
SCR
0111
D7
BIT 7
(MSB)
BIT 7
(MSB)
0
0
DIVISOR
LATCH
ACCESS
(DLAB)
0
0
DATA
CARRIER
DETECT
(DCD)
BIT 7
DATA BIT NUMBER
D6 D5 D4 D3 D2 D1 D0
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ENABLE
0
0
8250A/
16C450
INTERRUPT
000
SET
BREAK
STICK
PARITY
EVEN
PARITY
SELECT
(EPS)
0 0 LOOP
TRANSMIT
SHIFT REG
EMPTY
(TSRE)
TRANSMIT
HOLDING
REGISTER
EMPTY(THRE)
BREAK
INTERRUPT
(BI)
RING
INDICATOR
(RI)
DATA
SET READY
(DSR)
CLEAR
TO SEND
(CTS)
ENABLE
MODEM
STATUS
INTERRUPT
0
PARITY
ENABLE
(PEN)
ENABLE
INTERRUPT
(OUT2 IN
16C450)
FRAMING
ERROR
(FE)
DELTA
DATA CARR.
DETECT
(DDCD)
ENABLE
REC. LINE
STATUS
INTERRUPT
INTERRUPT
ID
BIT 1
NUMBER
OF STOP
BITS
(STB)
PRST
(OUT1 IN
16C450)
PARITY
ERROR
(PE)
TRAILING
EDGE RING
INDICATOR
(TERI)
ENABLE
THR
EMPTY
INTERRUPT
INTERRUPT
ID
BIT 0
WORD
LENGTH
SELECT 1
(WLS1)
REQUEST
TO SEND
(RTS)
OVERRUN
ERROR
(OE)
DELTA
DATA SET
READY
(DDSR)
ENABLE
REC. DATA
AVAILABLE
INTERRUPT
"0" IF
INTERRUPT
PENDING
WORD
LENGTH
SELECT 0
(WLS0)
DATA
TERMINAL
READY
(DTR)
DATA
READY
(DR)
DELTA
CLEAR
TO SEND
(DCTS)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DIVISOR
LATCH
(LS)
DLL
0000
DLAB = 1
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
DIVISOR
LATCH
(MS)
DLM
0001
DLAB = 1
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
* In single-port mode (STNDLN pin = 1), all four address lines UA3-UA0 are used to address the UART Control Registers.
* In dual-port mode (STNDLN pin = 0), only three address lines UA2-UA0 are used to address the UART Control Registers,
the UA3 pin becomes the MA2 pin in this mode.
BIT 1
BIT 9
BIT 0
BIT 8
11

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