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PDF 6B273 Data sheet ( Hoja de datos )
| Número de pieza | 6B273 | |
| Descripción | 8-BIT LATCHED DMOS POWER DRIVER | |
| Fabricantes | Allegro MicroSystems | |
| Logotipo |  |
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6B273
ADVANCE INFORMATION
(Subject to change without notice)
January 24, 2000
CLEAR 1
IN 1 2
IN 2 3
OUT 1 4
OUT2 5
OUT 3 6
OUT4 7
IN 3 8
IN 4 9
GROUND 10
VDD 20
LOGIC
SUPPLY
19 IN 8
18 IN 7
17 OUT8
16 OUT7
15 OUT6
14 OUT 5
13 IN 6
12 IN 5
11 STROBE
Dwg. PP-015-2
Note that the A6B273KA (DIP) and the A6B273KLW
(SOIC) are electrically identical and share a common
terminal number assignment.
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Output Voltage, VO ............................... 50 V
Output Drain Current,
Continuous, IO .......................... 150 mA*
Peak, IOM ................................... 500 mA†
Single-Pulse Avalanche Energy,
EAS ................................................. 30 mJ
Logic Supply Voltage, VDD .................. 7.0 V
Input Voltage Range,
VI ................................... -0.3 V to +7.0 V
Package Power Dissipation,
PD ........................................... See Graph
Operating Temperature Range,
TA ................................. -40°C to +125°C
Storage Temperature Range,
TS ................................. -55°C to +150°C
* Each output, all outputs on.
† Pulse duration ≤ 100 µs, duty cycle ≤ 2%.
Caution: These CMOS devices have input static
protection (Class 3) but are still susceptible to damage if
exposed to extremely high static electrical charges.
8-BIT LATCHED
DMOS POWER DRIVER
The A6B273KA and A6B273KLW combine eight (positive-edge-
triggered D-type) data latches and DMOS outputs for systems requiring
relatively high load power. Driver applications include relays, sole-
noids, and other medium-current or high-voltage peripheral power
loads. The CMOS inputs and latches allow direct interfacing with
microprocessor-based systems. Use with TTL may require appropriate
pull-up resistors to ensure an input logic high.
The DMOS output inverts the DATA input. All of the output
drivers are disabled (the DMOS sink drivers turned OFF) with the
CLEAR input low. The A6B273KA/KLW DMOS open-drain outputs
are capable of sinking up to 500 mA. Similar devices with reduced
rDS(on) are available as the A6273KA/KLW.
The A6B273KA is furnished in a 20-pin dual in-line plastic
package. The A6B273KLW is furnished in a 20-lead wide-body,
small-outline plastic package (SOIC) with gull-wing leads for surface-
mount applications. Copper lead frames, reduced supply current
requirements, and low on-state resistance allow both devices to sink
150 mA from all outputs continuously, to ambient temperatures over
85°C.
FEATURES
s 50 V Minimum Output Clamp Voltage
s 150 mA Output Current (all outputs simultaneously)
s 5 Ω Typical rDS(on)
s Low Power Consumption
s Replacements for TPIC6B273N and TPIC6B273DW
Always order by complete part number:
Part Number
A6B273KA
A6B273KLW
Package
20-pin DIP
20-lead SOIC
RθJA
55°C/W
70°C/W
RθJC
25°C/W
17°C/W
1 page  
6B273
8-BIT LATCHED
DMOS POWER DRIVER
TIMING REQUIREMENTS
INx
STROBE
OUTPUTx
50%
t su(D) t h(D)
50%
t PLH
10%
tr
50%
t su(D) t h(D)
t PHL
90%
tf
Dwg. WP-036-1
Input Active Time Before Strobe
(Data Set-Up Time), tsu(D) .............................................. 20 ns
Input Active Time After Strobe
(Data Hold Time), th(D) ................................................... 20 ns
Input Pulse Width, tw(D) ....................................................... 40 ns
Input Logic High, VIH ................................................ ≥ 0.85VCC
Input Logic Low, VIL ................................................. ≤ 0.15VCC
www.allegromicro.com
5 Page 
6B273
8-BIT LATCHED
DMOS POWER DRIVER
A6B273KLW
Dimensions in Inches
(for reference only)
20 11
0.0125
0.0091
0.2992
0.2914
0.020 1 2 3
0.013
0.5118
0.4961
0.050
BSC
0.419
0.394
0.050
0.016
0° TO 8°
0.0926
0.1043
0.0040 MIN.
20
Dwg. MA-008-20 in
Dimensions in Millimeters
(controlling dimensions)
11
0.32
0.23
7.60
7.40
0.51 1 2 3
0.33
13.00
12.60
1.27
BSC
10.65
10.00
1.27
0.40
0° TO 8°
2.65
2.35
0.10 MIN.
Dwg. MA-008-20 mm
NOTES: 1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
www.allegromicro.com
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet 6B273.PDF ] | |
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