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PDF 6A259 Data sheet ( Hoja de datos )

Número de pieza 6A259
Descripción 8-BIT ADDRESSABLE DMOS POWER DRIVER
Fabricantes Allegro MicroSystems 
Logotipo Allegro MicroSystems Logotipo



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6A259
ADVANCE INFORMATION
(Subject to change without notice)
March 22, 2000
A6A259KA (DIP)
OUT2 1
OUT3 2
S1
LOGIC
GROUND
POWER
GROUND
POWER
GROUND
3
4
5
6
S2 (MSB) 7
ENABLE 8 EN
OUT4 9
OUT5 10
20 OUT1
19 OUT0
18
VDD 17
16
15
S0 (LSB)
LOGIC
SUPPLY
POWER
GROUND
POWER
GROUND
14 CLEAR
13 DATA
12 OUT7
11 OUT6
Dwg. PP-050-4
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Output Voltage, VO ............................ 50 V
Output Drain Current,
Continuous, IO ...................... 350 mA*
Peak, IOM ........................... 1100 mA*†
Peak, IOM .................................... 2.0 A†
Single-Pulse Avalanche Energy,
EAS ............................................. 75 mJ
Logic Supply Voltage, VDD .............. 7.0 V
Input Voltage Range,
VI ............................... -0.3 V to +7.0 V
Package Power Dissipation,
PD ....................................... See Graph
Operating Temperature Range,
TA ............................. -40°C to +125°C
Storage Temperature Range,
TS ............................. -55°C to +150°C
*Each output, all outputs on.
† Pulse duration 100 µs, duty cycle 2%.
Caution: These CMOS devices have input static
protection (Class 3) but are still susceptible to dam-
age if exposed to extremely high static electrical
charges.
8-BIT ADDRESSABLE
DMOS POWER DRIVER
The A6A259KA and A6A259KLB combine a 3-to-8 line CMOS
decoder and accompanying data latches, control circuitry, and DMOS
outputs in a multi-functional power driver capable of storing single-line
data in the addressable latches or use as a decoder or demuliplexer.
Driver applications include relays, solenoids, and other medium-current
or high-voltage peripheral power loads.
The CMOS inputs and latches allow direct interfacing with micro-
processor-based systems. Use with TTL may require appropriate pull-
up resistors to ensure an input logic high. Four modes of operation are
selectable with the CLEAR and ENABLE inputs.
The addressed DMOS output inverts the DATA input with all
unaddressed outputs remaining in their previous states. All of the output
drivers are disabled (the DMOS sink drivers turned off) with the
CLEAR input low and the ENABLE input high. The A6A259KA/KLB
DMOS open-drain outputs are capable of sinking up to 500 mA.
The A6A259KA is furnished in a 20-pin dual in-line plastic pack-
age. The A6A259KLB is furnished in a 24-lead wide-body, small-
outline plastic batwing package (SOIC) with gull-wing leads for surface-
mount applications. Copper lead frames, reduced supply current re-
quirements, and low on-state resistance allow both devices to sink 150
mA from all outputs continuously, to ambient temperatures over 85°C.
FEATURES
I 50 V Minimum Output Clamp Voltage
I 350 mA Output Current (all outputs simultaneously)
I 1 Typical rDS(on)
I Internal Short-Circuit Protection
I Low Power Consumption
I Replacements for TPIC6A259N and TPIC6A259DW
Always order by complete part number:
Part Number Package
RθJA
A6A259KA 20-pin DIP 55°C/W
A6A259KLB 24-lead SOIC 55°C/W
RθJC
25°C/W
RθJT
6°C/W

1 page




6A259 pdf
6A259
8-BIT ADDRESSABLE
DMOS POWER DRIVER
FUNCTIONAL DESCRIPTION and INPUT REQUIREMENTS
ENABLE
DATA
ADDRESSED
OUTPUT
50%
t PLH
10%
tr
t PHL
90%
tf
OUTPUT SWITCHING TIME
Dwg. WP-036
ENABLE
DATA
50%
t su(D)
t h(D)
50%
t w(D)
DATA INPUT REQUIREMENTS
Dwg. WP-037
Data Active Time Before Enable
(Data Set-Up Time), tsu(D) .............................................. 20 ns
Data Active Time After Enable
(Data Hold Time), th(D) ................................................... 20 ns
Data Pulse Width, tw(D) ....................................................... 40 ns
Input Logic High, VIH ................................................ 0.85VDD
Input Logic Low, VIL ................................................. 0.15VDD
Four modes of operation are selectable by controlling the
CLEAR and ENABLE inputs as shown above.
In the addressable-latch mode, data at the DATA input is
written into the addressed transparent latch. The addressed
output inverts the data input with all other outputs remaining
in their previous states.
In the memory mode, all outputs remain in their previous
states and are unaffected by the DATA or address (Sn) inputs.
To prevent entering erroneus data in the latches, ENABLE
should be held HIGH while the address lines are changing.
In the demultiplexing/decoding mode, the addressed
output inverts the data input and all other outputs are OFF.
In the clear mode, all outputs are OFF and are unaffected
by the DATA or address (SN) inputs.
Given the appropriate inputs, when DATA is LOW for a
given address, the output is OFF; when DATA is HIGH, the
output is ON and can sink current.
LOGIC SYMBOL
S0
S1
S2
ENABLE
DATA
CLEAR
0
8M 0/7
2
G8
Z9
Z10
9,0D
10,0R
9,1D
10,1R
9,2D
10,2R
9,3D
10,3R
9,4D
10,4R
9,5D
10,5R
9,6D
10,6R
9,7D
10,7R
OUT 0
OUT 1
OUT 2
OUT 3
OUT 4
OUT 5
OUT 6
OUT 7
Dwg. FP-046-2
www.allegromicro.com

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