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PDF 74AC11377 Data sheet ( Hoja de datos )

Número de pieza 74AC11377
Descripción OCTAL D TYPE FLIP FLOP WITH ENABLE
Fabricantes NXP Semiconductors 
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74AC11374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS214A – JULY 1987 – REVISED APRIL 1996
D Eight D-Type Flip-Flops in a Single Package
D 3-State Bus-Driving True Outputs
D Full Parallel Access for Loading
D Flow-Through Architecture Optimizes
PCB Layout
D Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
D EPICt (Enhanced-Performance Implanted
CMOS) 1-mm Process
D 500-mA Typical Latch-Up Immunity at
125°C
D Package Options Include Plastic
Small-Outline (DW) and Shrink
Small-Outline (DB) Packages, and Standard
Plastic 300-mil DIPs (NT)
DB, DW, OR NT PACKAGE
(TOP VIEW)
1Q
2Q
3Q
4Q
GND
GND
GND
GND
5Q
6Q
7Q
8Q
1
2
3
4
5
6
7
8
9
10
11
12
24 OE
23 1D
22 2D
21 3D
20 4D
19 VCC
18 VCC
17 5D
16 6D
15 7D
14 8D
13 CLK
description
This 8-bit flip-flop features 3-state outputs designed specifically for driving highly-capacitive or relatively
low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers.
The eight flip-flops of the 74AC11374 are edge-triggered D-type flip-flops. On the positive transition of the clock,
the Q outputs are set to the logic levels set up at the D inputs.
The output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low
logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus
lines signigicantly. The high-impedance third state provides the capability to drive the bus lines in a
bus-organized system without need for interface or pullup components.
OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The 74AC11374 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OE CLK D
OUTPUT
Q
LH
H
LL
L
LLX
LHX
LX
HXX
Q0
Q0
Q0
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1996, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1

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74AC11377 pdf
74AC11374
OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS214A – JULY 1987 – REVISED APRIL 1996
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TA = 25°C
MIN TYP MAX
MIN MAX UNIT
fmax
tPLH
tPHL
CLK
Any Q
75 90
75 MHz
1.5 9.5 12.5 1.5 14.2
ns
1.5
9 12.6 1.5
14
tPZH
tPZL
tPHZ
tPLZ
OE
OE
Any Q
Any Q
1.5 8 10.9 1.5 12.3
ns
1.5 8 11.1 1.5 12.3
1.5 10 12.1 1.5 12.5
ns
1.5 8 10.7 1.5 11.6
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TA = 25°C
MIN TYP MAX
MIN MAX UNIT
fmax
tPLH
tPHL
CLK
Any Q
95 110
95 MHz
1.5 6.5
9 1.5 10.2
ns
1.5 5.5 9.1 1.5 10.1
tPZH
tPZL
tPHZ
tPLZ
OE
OE
Any Q
Any Q
1.5 5.5
8 1.5 9.1
ns
1.5 5.5 8.4 1.5 9.4
1.5 9 11 1.5 11.2
ns
1.5 6 8.6 1.5 9.2
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd Power dissipation capacitance per flip-flop
Outputs enabled
Outputs disabled
TEST CONDITIONS
CL = 50 pF
f =1 MHz
TYP UNIT
75
pF
66
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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