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PDF 74AC109MTC Data sheet ( Hoja de datos )

Número de pieza 74AC109MTC
Descripción Dual JK Positive Edge-Triggered Flip-Flop
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



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No Preview Available ! 74AC109MTC Hoja de datos, Descripción, Manual

74AC109, 74ACT109
Dual JK Positive Edge-Triggered Flip-Flop
March 2007
tm
Features
ICC reduced by 50%
Outputs source/sink 24mA
ACT109 has TTL-compatible inputs
General Description
The AC/ACT109 consists of two high-speed completely
independent transition clocked JK flip-flops. The clocking
operation is independent of rise and fall times of the
clock waveform. The JK design allows operation as a
D-Type flip-flop (refer to AC/ACT74 data sheet) by
connecting the J and K inputs together.
Asynchronous Inputs:
– LOW input to SD (Set) sets Q to HIGH level
– LOW input to CD (Clear) sets Q to LOW level
– Clear and Set are independent of clock
– Simultaneous LOW on CD and SD makes both
Q and Q HIGH
Ordering Information
Order
Number
74AC109SC
74AC109SJ
74AC109MTC
Package
Number
M16A
M16D
MTC16
74ACT109SC
74AC109MTC
M16A
MTC16
74ACT109PC
N16E
Package Description
www.DataSheet4U.com
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Connection Diagram
Pin Descriptions
Pin Names
J1, J2, K1, K2
CP1, CP2
CD1, CD2
SD1, SD2
Q1, Q2, Q1, Q2
Description
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
FACT™ is a trademark of Fairchild Semiconductor Corporation.
©1988 Fairchild Semiconductor Corporation
74AC109, 74ACT109 Rev. 1.5
www.fairchildsemi.com

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74AC109MTC pdf
DC Electrical Characteristics for ACT
Symbol
VIH
Parameter
Minimum HIGH
Level Input Voltage
VIL Maximum LOW
Level Input Voltage
VOH Minimum HIGH
Level Output
Voltage
VOL Maximum LOW
Level Output
Voltage
IIN
ICCT
IOLD
IOHD
ICC
Maximum Input
Leakage Current
Maximum ICC/Input
Minimum Dynamic
Output Current(5)
Maximum
Quiescent Supply
Current
VCC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
4.5
5.5
5.5
Conditions
VOUT = 0.1V or
VCC – 0.1V
VOUT = 0.1V or
VCC – 0.1V
IOUT = –50µA
VIN = VIL or VIH:
IOH = –24mA
IOH = –24mA(4)
IOUT = 50µA
VIN = VIL or VIH:
IOL = 24mA
IOL = 24mA(4)
VI = VCC, GND
TA = +25°C TA = –40°C to +85°C
Typ.
Guaranteed Limits
1.5 2.0
2.0
1.5 2.0
2.0
1.5 0.8
0.8
1.5 0.8
0.8
4.49 4.4
4.4
5.49 5.4
5.4
0.001
0.001
3.86
4.86
0.1
0.1
3.76
4.76
0.1
0.1
0.36
0.36
±0.1
0.44
0.44
± 1.0
5.5 VI = VCC – 2.1V
0.6
5.5 VOLD = 1.65V Max.
VOHD = 3.85V Min.
5.5 VIN = VCC or GND
2.0
1.5
75
–75
20.0
Notes:
4. All outputs loaded; thresholds on input associated with output under test.
5. Maximum test duration 2.0ms, one output loaded at a time.
Units
V
V
V
V
µA
mA
mA
mA
µA
©1988 Fairchild Semiconductor Corporation
74AC109, 74ACT109 Rev. 1.5
5
www.fairchildsemi.com

5 Page





74AC109MTC arduino
Physical Dimensions (Continued)
Dimensions are in inches (millimeters) unless otherwise noted.
Figure 4. 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N16E
©1988 Fairchild Semiconductor Corporation
74AC109, 74ACT109 Rev. 1.5
11
www.fairchildsemi.com

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